Patents by Inventor Chen Yang

Chen Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240151948
    Abstract: A photographing optical lens assembly includes, in order from an object side to an image side along an optical axis, a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element has positive refractive power. The second lens element has negative refractive power. The third lens element has an object-side surface being convex in a paraxial region thereof.
    Type: Application
    Filed: January 17, 2024
    Publication date: May 9, 2024
    Inventors: Cheng-Chen LIN, Hsin-Hsuan HUANG, Shu-Yun YANG
  • Publication number: 20240152193
    Abstract: The invention provides a power supply including at least one power output port, at least one status alert component, and at least one output port status monitoring module. The status alert component generates at least one visual prompt based on an alert signal. The output port status monitoring module includes at least one temperature sensor adjacent to the power output port, a microcontroller connected to the temperature sensor and sensing an output current from the power output port, and a reset signal generator connected to the microcontroller. The microcontroller comprises at least one port status alert condition that takes a temperature and the output current of the power output port as decision factors. The microcontroller outputs the alert signal to the status alert component when the port status alert condition is met and maintains the status until a reset signal provided by the reset signal generator is received.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 9, 2024
    Inventors: Wei-Chen WU, Wen-Hau HU, Hung-Wei YANG, Cheng-Yung LO, Yu-Hao SU, Jian-Zhi HUANG
  • Patent number: 11978640
    Abstract: In a method of forming a pattern over a semiconductor substrate, a target layer to be patterned is formed over a substrate, a mask pattern including an opening is formed in a mask layer, a shifting film is formed in an inner sidewall of the opening, a one-directional etching operation is performed to remove a part of the shifting film and a part of the mask layer to form a shifted opening, and the target layer is patterned by using the mask layer with the shifted opening as an etching mask. A location of the shifted opening is laterally shifted from an original location of the opening.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: May 7, 2024
    Inventors: Yi-Chen Lo, Yi-Shan Chen, Chih-Kai Yang, Pinyen Lin
  • Patent number: 11978115
    Abstract: A method for transferring a credit rights certificate is provided, including: generating a target account address according to a debtor account address and a creditor account address in a credit rights certificate transfer request, the target account address being a temporary account address used for storing a credit rights certificate and based on a multi-digital-signature process; transferring a credit rights certificate corresponding to the credit rights certificate transfer request from the debtor account address to the target account address; and transferring the credit rights certificate from the target account address to the creditor account address based on a confirmation instruction from the creditor account address.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: May 7, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Rui Guo, Yige Cai, Maocai Li, Qing Qin, Jianjun Zhang, Zongyou Wang, Zichao Tang, Qingzheng Shang, Chen Yang, Li Kong
  • Patent number: 11977687
    Abstract: The present invention provides a virtual keyboard for inputting Chinese characters and a configuring method thereof, an input method, and a Chinese character input system. The configuring method includes the following steps: setting a geometric layout of the virtual keyboard; and setting initials and finals on available keys of the virtual keyboard respectively using a cost function-based search algorithm so as to obtain an optimal layout of initial keys and final keys, wherein the initial keys and the final keys in the optimal layout are set based on a minimum cost function value for spelling all Chinese syllables, and the minimum cost function value is a minimum sum of weighted distances of the initial keys and the final keys for all the Chinese syllables.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: May 7, 2024
    Assignee: Tsinghua University
    Inventors: Xiaorong Gao, Bingchuan Liu, Xinyi Yan, Chen Yang, Shuming Xu
  • Patent number: 11978722
    Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate. The chip structure has an inclined sidewall, the inclined sidewall is at an acute angle to a vertical, the vertical is a direction perpendicular to a main surface of the chip structure, and the acute angle is in a range from about 12 degrees to about 45 degrees. The method also includes forming a protective layer to surround the chip structure.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Shen Yeh, Po-Chen Lai, Che-Chia Yang, Li-Ling Liao, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11978598
    Abstract: A keyswitch structure includes a base, a keycap, a lift mechanism and a light-emitting part. The lift mechanism includes a first support, a second support, and a spring structure. The first support and the second support are connected to and between the base and the keycap, so that the keycap can move relative to the base in a vertical direction. The spring structure is a single structural part and is connected to the first support and the second support and drives the first support and the second support to lift the keycap in the vertical direction. The lift mechanism as a whole defines a central space that extends through the whole lift mechanism in the vertical direction. The spring structure does not enter the central space. The light-emitting part is disposed on the base corresponding to the central zone, and emits light to illuminate the keycap.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: May 7, 2024
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Chen Yang, Ling-Hsi Chao, Shao-Lun Hsiao, Yu-Chun Hsieh
  • Publication number: 20240145381
    Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu
  • Publication number: 20240145554
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 2, 2024
    Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
  • Publication number: 20240146868
    Abstract: Embodiments of this disclosure relate to the multimedia processing field, and provide a video frame interpolation method, apparatus, and a device. In the video frame interpolation method in this disclosure, a first image at first time, a second image at second time, and sensor data captured by a dynamic vision sensor apparatus are obtained, and the sensor data includes dynamic event data between the first time and the second time. At least one target image is determined based on the first image, the second image, and the sensor data, where the at least one target image is an image corresponding to at least one target time between the first time and the second time. The dynamic event data is used to help compensate for motion information missing from existing image data. This implements accurate prediction of an intermediate image, and improves image prediction effect.
    Type: Application
    Filed: December 20, 2023
    Publication date: May 2, 2024
    Inventors: Ziyang ZHANG, Weihua HE, Chen YANG, Jianxing LIAO, Kun TIAN, Ying WANG, Yunlong ZHAN
  • Patent number: 11973429
    Abstract: The resonant tank circuit (102) comprises: a transformer (T); a primary circuit (M1); and a secondary circuit (M2); wherein the transformer (T) and the primary and secondary circuits (M1, M2) are designed to operate in a forward mode and in a reverse mode; and wherein the transformer (T) and the primary and secondary circuits (M1, M2) have, at a resonant frequency (FR), a forward gain (GF(FR)), respectively a reverse gain (GR(FR)), essentially independent of the load, when operating in the forward mode, respectively the reverse mode. The primary and secondary circuits (M1, M2) are different one from another and the forward gain (GF(FR)) and the reverse gain (GR(FR)) at the resonant frequency (FR) are essentially equal to one another, notably to within 5%.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: April 30, 2024
    Inventors: Chen He, Gang Yang
  • Publication number: 20240133745
    Abstract: A temperature sensing device includes a substrate, a first reflective module, a first window cover, and a dual thermopile sensor. The first reflective module is disposed on the substrate, including a first mirror chamber with a narrow field of view (FOV), and the first reflective module focuses a thermal radiation from measured object to a first image plane in the first mirror chamber. The first window cover is disposed on the first reflective module, and the first window cover allows a selected band of the thermal radiation to pass through. The dual thermopile sensor is disposed on the substrate and located in the first mirror chamber, and the dual thermopile sensor senses a temperature data from the first image plane. Additional second reflective module, LED source plus pin hole with same FOV of dual thermopile sensor can illuminate the measured object for ease of placement of object to be heated.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 25, 2024
    Inventors: Chein-Hsun WANG, Ming LE, Tung-Yang LEE, Yu-Chih LIANG, Wen-Chie HUANG, Chen-Tang HUANG, Jenping KU
  • Publication number: 20240136291
    Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.
    Type: Application
    Filed: January 12, 2023
    Publication date: April 25, 2024
    Inventors: Hsiang-Ku SHEN, Chen-Chiu HUANG, Chia-Nan LIN, Man-Yun WU, Wen-Tzu CHEN, Sean YANG, Dian-Hao CHEN, Chi-Hao CHANG, Ching-Wei LIN, Wen-Ling CHANG
  • Publication number: 20240136742
    Abstract: A connector assembly includes a shielding cage, a partitioning assembly and a plurality of supporting members. The shielding cage has a plurality of walls and an internal space defined by the plurality of walls, the plurality of walls includes two side walls. The partitioning assembly is assembled to the two side walls of the shielding cage and partitions the internal space into two inserting chambers arranged up and down, the partitioning assembly includes two partitioning plates which are arranged up and down and two grounding elastic pieces which are respectively assembled to front ends of the two partitioning plates, the two partitioning plates are spaced apart from with each other by a preset interval to together constitute an air flow passageway and a front end opening positioned to a front end of the air flow passageway. The plurality of supporting members are supported between the two partitioning plates.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 25, 2024
    Inventors: Hui- Hsuan Yang, Bhakteesh Arwankar, Weiming Chen, Saiyed Muhammad Hasan Ali
  • Publication number: 20240135918
    Abstract: A method includes receiving distillation data including a plurality of out-of-domain training utterances. For each particular out-of-domain training utterance of the distillation data, the method includes generating a corresponding augmented out-of-domain training utterance, and generating, using a teacher ASR model trained on training data corresponding to a target domain, a pseudo-label corresponding to the corresponding augmented out-of-domain training utterance. The method also includes distilling a student ASR model from the teacher ASR model by training the student ASR model using the corresponding augmented out-of-domain training utterances paired with the corresponding pseudo-labels generated by the teacher ASR model.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 25, 2024
    Applicant: Google LLC
    Inventors: Tien-Ju Yang, You-Chi Cheng, Shankar Kumar, Jared Lichtarge, Ehsan Amid, Yuxin Ding, Rajiv Mathews, Mingqing Chen
  • Publication number: 20240136213
    Abstract: In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Chun-Jung HUANG, Yung-Lin HSU, Kuang Huan HSU, Jeff CHEN, Steven HUANG, Yueh-Lun YANG
  • Publication number: 20240136313
    Abstract: An electrical connection includes a first driving substrate, a first adhesive layer, a first bonding pad a first bonding pad and a second bonding pad. The first driving substrate includes a first substrate and a first dielectric layer on the first substrate. The first adhesive layer is at a sidewall of the first dielectric layer of the first driving substrate. The first bonding pad is on the first substrate of the first driving substrate and in contact with the first adhesive layer, and the first bonding pad includes a plurality of grains, the grains are connected with each other, the grains include [111]-oriented copper grains, and a maximum width of the first bonding pad is equal to or less than 8 microns. The second bonding pad is on the first bonding pad.
    Type: Application
    Filed: July 6, 2023
    Publication date: April 25, 2024
    Inventors: Chih CHEN, Shih-Chi YANG
  • Publication number: 20240134689
    Abstract: A hardware functional module performs a given task. A first notification that the given task has completed and which includes a scoreboard identifier is sent to a scoreboard module. The scoreboard module selects a scoreboard counter based on the scoreboard identifier. The selected scoreboard counter is incremented. It is determined whether the selected scoreboard counter exceeds a corresponding scoreboard threshold. If the selected scoreboard counter exceeds the corresponding scoreboard threshold, a second notification indicating that the plurality of tasks has completed is sent. If the scoreboard identifier corresponds to the host command module, the second notification is sent to the host command module. If the scoreboard identifier corresponds to the backend command module, the second notification is sent to the backend command module.
    Type: Application
    Filed: November 9, 2023
    Publication date: April 25, 2024
    Inventors: Priyanka Nilay Thakore, Chen Xiu, Lyle E. Adams, Deqiang Yang
  • Publication number: 20240138152
    Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Feng-Cheng Yang, Meng-Han Lin, Sheng-Chen Wang, Han-Jong Chia, Chung-Te Lin
  • Patent number: D1025940
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: May 7, 2024
    Inventors: Ziao Wang, Chen Zhu, Yang Yang