Patents by Inventor Chen-Yu (Sean) Lin
Chen-Yu (Sean) Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12317462Abstract: In a method of manufacturing an electronic package, first grooves are formed on a circuit structure and a second groove is formed in each of the first grooves to allow the circuit structure to become circuit layers. Owing to the second groove is narrower than the first groove, each of the circuit layers has an encircled surface and a notch located on the encircled surface. When a shielding layer is provided to cover an encapsulating body located on the circuit layer, a space of the notch is not covered by the shielding layer such that a portion to be removed of the shielding layer will not remain on the electronic package to become burr after removing the portion to be removed.Type: GrantFiled: July 13, 2023Date of Patent: May 27, 2025Assignee: CHIPBOND TECHNOLOGY CORPORATIONInventors: Chen-Yu Wang, Pai-Sheng Cheng, Huan-Kuen Chen
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Patent number: 12314072Abstract: A voltage generating device includes a low-dropout voltage regulator and a control signal generator. The low-dropout voltage regulator provides an output voltage to a power distribution network. The low-dropout voltage regulator has a feedback circuit. The feedback circuit divides the output voltage to generate a feedback voltage according to a voltage dividing ratio, and the feedback circuit sets the voltage dividing ratio according to multiple control signals. The control signal generator is coupled to the feedback circuit and the power distribution network, and generates the control signals by comparing a sensing voltage at a reference terminal of the power distribution network with multiple threshold voltages.Type: GrantFiled: December 15, 2022Date of Patent: May 27, 2025Assignee: Windbond Electronics Corp.Inventor: Chen-Yu Wu
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Publication number: 20250167149Abstract: A manufacturing method of a semiconductor structure is provided. The method includes: forming contact pads on an interconnect structure over a semiconductor substrate; forming a dielectric material stack on the interconnect structure; forming holes and a recess in the dielectric material stack to form a dielectric structure, wherein the holes accessibly expose portions of the contact pads, and the recess is formed between adjacent two of the holes; and forming conductive materials in the holes and the recess to respectively form bonding connectors and a dummy feature. The bonding connectors land on the contact pads, and the dummy feature is isolated and substantially equidistant from adjacent two of the bonding connectors.Type: ApplicationFiled: January 20, 2025Publication date: May 22, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yu Tsai, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20250163602Abstract: A plating apparatus includes a workpiece holder. a plating bath, and a clamp ring. The plating bath is underneath the workpiece holder. The clamp ring is connected to the workpiece holder. The clamp ring includes channels communicating an inner surface of the clamp ring and an outer surface of the clamp ring.Type: ApplicationFiled: January 20, 2025Publication date: May 22, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yu Tsai, Ku-Feng Yang, Wen-Chih Chiou
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Publication number: 20250155804Abstract: A photoresist composition comprises a solvent and a polymer. The polymer is dissolved in the solvent. The photoresist composition further comprises a first additive. The first additive is dissolved in the solvent. The first additive is made of a core structure and one or more radical-active functional groups connected to the core structure.Type: ApplicationFiled: November 14, 2023Publication date: May 15, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Min-Hung TSAI, Siao-Shan WANG, Chen-Yu LIU, Ching-Yu CHANG
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Publication number: 20250146644Abstract: A vehicle light has a heating element and a radiator vent that creates and distributes heated air inside the vehicle light. This prevents fog buildup on the inside of the light in cold and wet weather, allowing for more efficient and therefore safer lights for vehicles. A series of ceramic heating elements is arrayed in front of individual spines of a radiator vent. As each ceramic heating element receives electricity from the vehicle, its surface heats up. Air is blown past the heating elements and directed through the radiator vent by two or more blower motors. A temperature sensor regulates the amount of electricity that is sent to each ceramic element.Type: ApplicationFiled: November 7, 2024Publication date: May 8, 2025Applicant: Wheel Pros, LLCInventors: Matt Kossoff, Yoshitaka Ishida, Chen Yu
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Publication number: 20250147424Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.Type: ApplicationFiled: January 6, 2025Publication date: May 8, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Hui WENG, Chen-Yu LIU, Cheng-Han WU, Ching-Yu CHANG, Chin-Hsiang LIN
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Patent number: 12292684Abstract: A method is provided including forming a first layer over a substrate and forming an adhesion layer over the first layer. The adhesion layer has a composition including an epoxy group. A photoresist layer is formed directly on the adhesion layer. A portion of the photoresist layer is exposed to a radiation source. The composition of the adhesion layer and the exposed portion of the photoresist layer cross-link using the epoxy group. Thee photoresist layer is then developed (e.g., by a negative tone developer) to form a photoresist pattern feature, which may overlie the formed cross-linked region.Type: GrantFiled: December 7, 2020Date of Patent: May 6, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Yu Liu, Tzu-Yang Lin, Ya-Ching Chang, Ching-Yu Chang, Chin-Hsiang Lin
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Publication number: 20250139978Abstract: A vehicle violation detection method and vehicle violation detection system are provided. The method includes the following steps. A video clip including a plurality of consecutive frames is obtained, wherein the video clip is generated through photographing an intersection by an image capture device. A traffic sign object corresponding to a traffic sign and a license plate object corresponding to a license plate are detected from each of the frames. According to a sign position of the traffic sign object and a plate position of the license plate object in each of the frames, vehicle behavior information of each of the frames is obtained. By conducting regression analysis to the vehicle behavior information of each of the frames, whether a vehicle violation event has occurred is determined.Type: ApplicationFiled: November 9, 2023Publication date: May 1, 2025Applicant: National Chengchi UniversityInventors: Yan-Tsung Peng, Chen-Yu Liu, He-Hao Liao, Wei-Cheng Lien
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Publication number: 20250136739Abstract: A resin composition includes a polymer, which has a first structural unit of Formula (1) and a second structural unit of Formula (2). The resin composition may be used to make a prepreg, a resin film, a laminate or a printed circuit board, and at least one of the following properties can be improved, including dielectric constant, dissipation factor, copper foil peeling strength and warpage at high temperature.Type: ApplicationFiled: December 7, 2023Publication date: May 1, 2025Inventor: Chen-Yu HSIEH
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Publication number: 20250125716Abstract: A calibration circuit of a pulse-frequency modulation (PFM) converter includes a signal generator circuit and a calibration control circuit. The signal generator circuit generates and outputs an emulated slope signal to a comparator circuit under a calibration mode, wherein the emulated slope signal has an emulated slope following an initial voltage, and the emulated slope corresponds to a slope of a sensed signal indicative of electrical characteristic of an inductor of the PFM converter. The calibration control circuit refers to an output signal that is generated from a PFM control circuit in response to an output signal of the comparator circuit, to calibrate at least one circuit of the PFM converter.Type: ApplicationFiled: October 7, 2024Publication date: April 17, 2025Applicant: Airoha Technology Corp.Inventors: Chen-Yu Wang, Ke-Deng Huang
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Publication number: 20250127063Abstract: A magnetoresistive memory device and an integrated memory circuit are provided. The magnetoresistive memory device includes a magnetic tunneling junction (MTJ) and a composite spin orbit torque (SOT) channel in contact with a terminal of the MTJ. The SOT channel includes: a first channel layer, configured to convert a portion of a charge current into an orbital current based on orbital Hall effect; and a second channel layer, covering the first channel layer, and configured to convert a portion of the charge current into a first spin current based on spin Hall effect, and to convert the orbital current to a second spin current.Type: ApplicationFiled: October 11, 2023Publication date: April 17, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Yuan Song, Chi-Feng Pai, Xinyu BAO, Chen-Yu Hu
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Patent number: 12278203Abstract: A semiconductor structure including a first die, a second die stacked on the first die, a smoothing layer disposed on the first die and a filling material layer disposed on the smoothing layer. The second die has a dielectric portion and a semiconductor material portion disposed on the dielectric portion. The smoothing layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is disposed on the first dielectric layer. The dielectric portion is surrounded by the smoothing layer, and the semiconductor material portion is surrounded by the filling material layer. A material of the first dielectric layer is different from a material of the second dielectric layer and a material of the filling material layer.Type: GrantFiled: June 16, 2022Date of Patent: April 15, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yu Tsai, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 12273389Abstract: A method, computer system, and a computer program product for smart SDN is provided. The present invention may include recording and clustering a pod's behavior to generate a behavior transition model for the pod. The present invention may include watching a behavior of the pod and comparing the behavior to the generated behavior transition model. The present invention may include triggering a network policy change based on determining that the behavior of the pod is a misbehavior.Type: GrantFiled: March 22, 2022Date of Patent: April 8, 2025Assignee: International Business Machines CorporationInventors: Jeff Hsueh-Chang Kuo, June-Ray Lin, Ying-Chen Yu, Chih-Wen Su
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Publication number: 20250107082Abstract: A memory device includes a stack structure, a first stop layer, a dielectric layer, at least one separation wall and a conductive plug. The stacked structure is located over a substrate. The stacked structure has an opening exposing a stepped structure of the stacked structure. The first stop layer covers the stepped structure and at least at least one portion of sidewalls of the opening. The dielectric layer fills the opening and covers the first stop layer. The separation wall extends through the dielectric layer and the first stop layer in the opening. The conductive plug extends through the dielectric layer and the first stop layer, and is electrically connected to the stepped structure. The memory device may be a 3D NAND flash memory with high capacity and high performance.Type: ApplicationFiled: September 26, 2023Publication date: March 27, 2025Applicant: MACRONIX International Co., Ltd.Inventors: Chen-Yu Cheng, Chih-Kai Yang, Shih-Chin Lee, Tzung-Ting Han
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Publication number: 20250105213Abstract: Provided is a semiconductor device for manufacturing a 3D NAND flash memory with high capacity and high performance. The semiconductor device includes: a first device structure layer on a substrate; an interconnect structure layer on the first device structure layer, which includes first pads at a surface thereof; a second device structure layer on the interconnect structure layer, which includes second pads at a surface thereof; a pattern structure at an interface between the interconnect structure layer and the second device structure layer; a first seal ring at the surface of the interconnect structure layer, which surrounds the pattern structure; a second seal ring at the surface of the second device structure layer, which surrounds the pattern structure. The first pad is connected to the second pad, and the first seal ring is connected to the second seal ring.Type: ApplicationFiled: September 26, 2023Publication date: March 27, 2025Applicant: MACRONIX International Co., Ltd.Inventors: Shao-En Chang, Tzung-Ting Han, Meng-Hsuan Weng, Chen-Yu Cheng
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Patent number: 12262566Abstract: An optoelectronic module, including a substrate, a covering member, a light emitting element, and a light receiving element, is provided. The covering member is disposed on the substrate and includes an upper cover portion, a peripheral sidewall portion connected to the upper cover portion, and an inside partition delimiting a first cavity and a second cavity. The first cavity is separated from the second cavity. The light emitting element is disposed on the substrate as corresponding to the first cavity. The light receiving element is disposed on the substrate as corresponding to the second cavity. The inside partition has a first inner wall surface located in the first cavity and a second inner wall surface located in the second cavity. A first protruded-recessed structure is formed on the first inner wall surface.Type: GrantFiled: March 10, 2022Date of Patent: March 25, 2025Assignee: Life-On Technology CorporationInventors: Jui Lin Tsai, Chien Tien Wang, Shu-Hua Yang, Hsin Wei Tsai, You-Chen Yu
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Publication number: 20250091673Abstract: In one embodiment, a computer-implemented method includes collecting data from at least one component of a micromobility vehicle. The method includes analyzing the data to determine whether a condition of the micromobility vehicle corresponds to an unsafe condition. The method includes determining, based on analysis, that the condition of the micromobility vehicle corresponds to the unsafe condition. The method includes activating an immobilization lock on the micromobility vehicle to immobilize a wheel of the micromobility vehicle responsive to determining that the condition of the micromobility vehicle corresponds to the unsafe condition.Type: ApplicationFiled: December 2, 2024Publication date: March 20, 2025Inventors: Erik Keith Askin, Jeffrey Alan Boyd, Alex Dixon, Garrett Korda Drayna, Merric-Andrew Jaranowski French, Daniel Lami Goldstein, Rochus Emanuel Jacob, Jared Mitchell Kole, Chen-Yu Lin, Oliver Maximilian Mueller, James Jeng-Yeu Peng, Andrew Michael Reimer, Neil Richard Anthony Saldanha, Gary Shambat, Jennifer Uang
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Publication number: 20250094033Abstract: Disclosed are an edge tool configuration method and an electronic device. The edge tool configuration method includes: detecting a placement status of the electronic device through a sensor; reading configuration information of the edge tool according to the placement status, wherein the configuration information includes initial configuration information of the edge tool in a plurality of default placement statuses; placing the edge tool at an edge position in a display interface of a display according to the configuration information in the placement status.Type: ApplicationFiled: September 19, 2023Publication date: March 20, 2025Applicant: ASUSTeK COMPUTER INC.Inventors: Chia-In Liao, Chih-Hsien Yang, Li-Te Yang, Yung-Hsuan Kao, Chen-Yu Hsu, Shun-Wen Huang
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Publication number: 20250096584Abstract: An inlet for a charger is provided. The inlet includes a body, a first plate, a circuit board assembly, and a second plate. The first plate is disposed on the body. The first plate has a first hole. The circuit board assembly is disposed on the first plate. The circuit board assembly has a second hole. The second plate is disposed on the circuit board assembly. The body has a first pin. The first pin penetrates through the first hole and the second hole and is covered by the second plate.Type: ApplicationFiled: January 9, 2024Publication date: March 20, 2025Inventors: Chen-Yu TSAI, Yu-Po Chen