Patents by Inventor Chen-Yu (Sean) Lin

Chen-Yu (Sean) Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240385514
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hui WENG, Chen-Yu LIU, Chih-Cheng LIU, Yi-Chen KUO, Jia-Lin WEI, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • Publication number: 20240389472
    Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5 d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3 d orbitals.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Yen-Lin Huang, MingYuan Song, Chien-Min Lee, Shy-Jay Lin, Chi-Feng Pai, Chen-Yu Hu, Chao-Chung Huang, Kuan-Hao Chen, Chia-Chin Tsai, Yu-Fang Chiu, Cheng-Wei Peng
  • Publication number: 20240389213
    Abstract: A dispensing system includes a dispense material supply that contains a dispense material and a dispensing pump connected downstream from the dispense material supply. The dispensing pump includes a body made of a first electrically conductive material, one or more first electrical contacts that are disposed on the body of the dispensing pump, and one or more first connection wires that are coupled between each one of the one or more first electrical contacts and ground. The dispensing system also includes a dispensing nozzle connected downstream from the dispensing pump and includes a tube made of a second electrically conductive material, one or more second electrical contacts that are disposed on an outer surface of the tube, and one or more second connection wires that are coupled between each one of the one or more second electrical contacts and the ground.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yang LIN, Yu-Cheng CHANG, Cheng-Han WU, Shang-Sheng LI, Chen-Yu LIU, Chen Yi HSU
  • Patent number: 12147537
    Abstract: A malware family identification engine constructs a graph data structure of direct relationships between malware instances and malware families, direct relationships between malware instances and detected tags, and indirect relationships between detected tags and malware families. The engine builds a dictionary data structure comprising detected tag entries linking each detected tag to one or more malware family nodes based on the graph data structure. The engine identifies significant indirect entities (SIEs) within the detected tag entries of the dictionary data structure and selects a SIE with a highest number of out-going links (OGLs) as a root node in a family tree data structure, recursively connects SIEs with a number of OGLs less than the highest number of OGLs to the root node in the family tree data structure, and converts each SIE name in the family tree data structure to a chained family entity name in the family tree data structure.
    Type: Grant
    Filed: December 12, 2023
    Date of Patent: November 19, 2024
    Assignee: Business Machines Corporation
    Inventors: Yu-Siang Chen, Ci-Hao Wu, Ying-Chen Yu, Pao-Chuan Liao, June-Ray Lin
  • Patent number: 12146049
    Abstract: A styrene-isoprene/butadiene diblock copolymer contains a polystyrene block and a polyisoprene/butadiene block. Based on 100 wt % of the styrene-isoprene/butadiene diblock copolymer, the polystyrene block is 20-45 wt %, and the polyisoprene/butadiene block is 55-80 wt %. The polyisoprene/butadiene block has a polyisoprene unit and a polybutadiene unit. The weight ratio of the polyisoprene unit to the polybutadiene unit is 8:2 to 2:8.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: November 19, 2024
    Assignee: LCY CHEMICAL CORP.
    Inventors: Yi-Cheng Wan, Chen-Yu Wang
  • Publication number: 20240379565
    Abstract: Embodiments include a method for forming an integrated circuit package. A first dielectric layer is deposited over a wafer, the first dielectric layer overlapping a package region and a scribe line region of the wafer. A first metallization pattern is formed extending along and through the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern and the first dielectric layer, the second dielectric layer overlapping the package region and the scribe line region. The second dielectric layer is removed from the scribe line region, the second dielectric layer remaining in the package region. After the second dielectric layer is removed from the scribe line region, a second metallization pattern is formed extending along and through the second dielectric layer. The wafer and the first dielectric layer are sawed in the scribe line region.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 14, 2024
    Inventors: Wei-An Tsao, Chen Yu Wu, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20240366631
    Abstract: The present disclosure provides a method of treating or ameliorating an operative complication of a cataract surgery. The method comprises administering nanoparticles of clobetasol propionate to a subject in need thereof.
    Type: Application
    Filed: May 1, 2023
    Publication date: November 7, 2024
    Applicant: FORMOSA PHARMACEUTICALS, INC.
    Inventors: Chen Yu CHENG, Laurene WANG, Wei-Cheng LIAW, Derek Joseph Raphael NUNEZ
  • Publication number: 20240371804
    Abstract: A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Chen-Yu Tsai, Ku-Feng Yang, Wen-Chih Chiou
  • Publication number: 20240371638
    Abstract: A method of forming a pattern in a photoresist includes forming a photoresist layer over a substrate, and selectively exposing the photoresist layer to actinic radiation to form a latent pattern. The latent pattern is developed by applying a developer composition to the selectively exposed photoresist layer to form a pattern. The developer composition includes a first solvent, a second solvent, a surfactant, and at least one selected from an organic acid, an organic base, an inorganic acid, or an inorganic base. The first solvent and second solvent are different solvents.
    Type: Application
    Filed: July 12, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hui WENG, An-Ren ZI, Ching-Yu CHANG, Chen-Yu LIU
  • Publication number: 20240371979
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Inventors: Shih-Yao Lin, Pei-Hsiu Wu, Chih Ping Wang, Chih-Han Lin, Jr-Jung Lin, Yun Ting Chou, Chen-Yu Wu
  • Patent number: 12134159
    Abstract: A workpiece orientation mechanism includes: a driving device including a transmission motor and a controller which are connected with each other via signal, the transmission motor defining an axial direction; a rotating seat, combined with the transmission motor, and capable of being driven to rotate by the transmission motor; an orientation head disposed on the rotating seat to rotate synchronously with the rotating seat, wherein the orientation head is capable of moving along the axial direction relative to the rotating seat, one end of the orientation head includes a mounting head, and a blocking member is disposed on the orientation head; reset means, arranged between the rotating seat and the orientation head, and positioning the orientation head at a predetermined position; and a sensor facing the blocking member, wherein the sensor is signally connected with the controller.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: November 5, 2024
    Assignee: Hiwin Technologies Corp.
    Inventors: Chen-Yu Hsieh, Jhao-Jhong Su, Bo-Chen Lin, Kuo-Cheng Huang
  • Patent number: 12135501
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: November 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hui Weng, Chen-Yu Liu, Chih-Cheng Liu, Yi-Chen Kuo, Jia-Lin Wei, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
  • Patent number: 12135695
    Abstract: In an approach, a processor obtains a configuration file of a distributed file system federation, the configuration file comprising a list of a plurality of subclusters within the distributed file system federation and migration trigger factors for the plurality of subclusters. A processor determines a list of one or more source subclusters and a list of to-be-migrated directories in the one or more source subclusters based on a scanning result of the plurality of subclusters and the migration trigger factors in the configuration file. A processor generates a migration plan to migrate the to-be-migrated directories from the one or more source subclusters to one or more target subclusters in the distributed file system federation.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: November 5, 2024
    Assignee: International Business Machines Corporation
    Inventors: Jun Guo, Xiang Yu Yang, Deng Xin Luo, Na Liu, Chen Yu Chang, Qin Dong Yin
  • Publication number: 20240365568
    Abstract: Methods, systems and apparatus for three-dimensional (3D) memory devices are provided. In one aspect, a semiconductor device includes: an array-side structure and a device-side structure. The array-side structure includes a memory array of memory cells and an array-side integrated circuit conductively coupled to the memory array. The device-side structure includes a device-side integrated circuit. The array-side structure and the device-side structure are integrated together with one or more connection pads therebetween. The array-side integrated circuit and the device-side integrated circuit are conductively coupled to each other through at least one of the one or more connection pads and configured to perform one or more operations on the memory array.
    Type: Application
    Filed: April 26, 2023
    Publication date: October 31, 2024
    Applicant: Macronix International Co., Ltd.
    Inventors: Chen-Yu Cheng, Tzung-Ting Han
  • Patent number: 12132016
    Abstract: A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Yu Tsai, Ku-Feng Yang, Wen-Chih Chiou
  • Patent number: 12127856
    Abstract: The present disclosure relates to a difficult airway evaluation method and device based on a machine learning voice technology. The method includes the following steps: acquiring voice data of a patient; carrying out feature extraction on the voice data, obtaining a pitch period of pronunciations, and acquiring a voiced sound feature and unvoiced sound features based on the pitch period of pronunciations; and constructing a difficult airway evaluation classifier based on the machine learning voice technology, analyzing the received voiced sound feature and unvoiced sound features by the trained difficult airway evaluation classifier, and carrying out scoring on the severity of a difficult airway to obtain an evaluation result of the difficult airway.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: October 29, 2024
    Assignee: Shanghai Ninth People's Hospital, Shanghai Jiao Tong University School of Medicine
    Inventors: Hong Jiang, Ming Xia, Ren Zhou, Shuang Cao, Tian Yi Xu, Jie Wang, Chen Yu Jin, Bei Pei
  • Publication number: 20240354504
    Abstract: Systems and methods for providing a structure-aware sequence model that can interpret a document's text without first inferring the proper reading order of the document. In some examples, the model may use a graph convolutional network to generate contextualized “supertoken” embeddings for each token, which are then fed to a transformer that employs a sparse attention paradigm in which attention weights for at least some supertokens are modified based on differences between predicted and actual values of the order and distance between the attender and attendee supertokens.
    Type: Application
    Filed: August 25, 2021
    Publication date: October 24, 2024
    Inventors: Chen-Yu Lee, Chun-Liang Li, Timothy Dozat, Vincent Perot, Guolong Su, Nan Hua, Joshua Ainslie, Renshen Wang, Yasuhisa Fujii, Tomas Pfister
  • Publication number: 20240355732
    Abstract: A memory device includes first and second interconnect structures, a stacked structure, a stop layer and channel pillar structures over a substrate. The stacked structure is located between the first and the second interconnection structures. The stop layer is located between the stacked structure and the second interconnect structure. Each channel pillar structure includes a channel pillar, a first channel plug and a second channel plug. The channel pillar extends through the stacked structure and the stop layer. The first channel plug is located at a first end of the channel pillar and connected to the first interconnection structure. The second channel plug is located at a second end of the channel pillar and connected to the second interconnection structure. A bottom surface of the second channel plug is closer to the substrate than a bottom surface of the stop layer.
    Type: Application
    Filed: April 19, 2023
    Publication date: October 24, 2024
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Chen-Yu Cheng, Chih-Kai Yang, Tzung-Ting Han
  • Publication number: 20240347413
    Abstract: A semiconductor device assembly is provided. The semiconductor device assembly can include a substrate and one or more semiconductor dies. The semiconductor device assembly can further include a thermally conductive material (e.g., carbon nanotubes, graphene) capable of dissipating heat from the semiconductor device assembly. In doing so, a thermally regulated semiconductor device can be assembled.
    Type: Application
    Filed: March 14, 2024
    Publication date: October 17, 2024
    Inventors: Chen Yu Huang, Chong Leong Gan
  • Publication number: 20240348020
    Abstract: An energy storage management and control system comprising an cabinet and electrical components; the internal space of the cabinet is divided into a direct current high-voltage area, a low-voltage communication and control area, and an alternating current power distribution area; and the electrical components comprise a direct current high-voltage electrical component set in the direct current high-voltage area, a low-voltage electrical component and a communication and control electrical component set in the low-voltage communication and control area, and an alternating current power distribution component set in the alternating current power distribution area.
    Type: Application
    Filed: April 3, 2024
    Publication date: October 17, 2024
    Inventors: Hui CAO, Si LIU, Chen YU, Bangming ZHANG