Patents by Inventor Cheng Chi

Cheng Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and compositions for immunization against virus
    Patent number: 11672853
    Abstract: Immunogenic compositions comprising partially glycosylated viral glycoproteins for use as vaccines against viruses are provided. Vaccines formulated using mono-, di-, or tri-glycosylated viral surface glycoproteins and polypeptides provide potent and broad protection against viruses, even across strains. Pharmaceutical compositions comprising monoglycosylated hemagglutinin polypeptides and vaccines generated therefrom and methods of their use for prophylaxis or treatment of viral infections are disclosed. Methods and compositions are disclosed for influenza virus HA, NA and M2, RSV proteins F, G and SH, Dengue virus glycoproteins M or E, hepatitis C virus glycoprotein E1 or E2 and HIV glycoproteins gp120 and gp41.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: June 13, 2023
    Assignee: Academia Sinica
    Inventors: Chi-Huey Wong, Che Ma, Cheng-Chi Wang, Juine-Ruey Chen
  • DISPLAY DEVICES WITH PIVOT CONNECTIONS
    Publication number: 20230176619
    Abstract: An example computing device includes a body and a first display device including a lower end that is pivotably connected to the body and a front surface including a first display area. The computing device further includes a second display device including a pivotable end that is pivotably connected to the body and a free end opposite the pivotable end. The computing device further includes a bias member connecting the second display device to the first display device. The bias member resiliently urges the free end of the second display device towards the front surface of the first display device.
    Type: Application
    Filed: April 30, 2020
    Publication date: June 8, 2023
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Mark David Senatori, Dong Ryul Cha, Cheng Chi Cheng
  • Interconnect structure
    Patent number: 11670581
    Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a source/drain (S/D) feature formed in an interlayer dielectric layer (ILD), a S/D contact via electrically connected to the S/D feature, a metal feature formed over the S/D contact via, and a metal line formed over the metal feature and electrically connected to the S/D contact via. The metal line is formed of a material different from that of the S/D contact via, and the S/D contact via is spaced apart from the metal line. By providing the metal feature, electromigration between the metal line and the contact via may be advantageously reduced or substantially eliminated.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Method for forming source/drain contacts utilizing an inhibitor
    Patent number: 11670691
    Abstract: A device includes a substrate, a gate structure over the substrate, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer, wherein a bottom surface of the dielectric liner is spaced away from the silicide by a gap, and an S/D contact over the silicide and at least partially filling the gap.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Semiconductor devices with backside air gap dielectric
    Patent number: 11664280
    Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain electrodes; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside, wherein the two metal plugs and the isolation structure form sidewalls of a trench; and a dielectric liner on the sidewalls of the trench, wherein the dielectric liner partially or fully surrounds an air gap within the trench.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yuan Chen, Huan-Chieh Su, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Semiconductor device with L-shape conductive feature and methods of forming the same
    Patent number: 11664278
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Chi Chuang, Li-Zhen Yu, Yi-Hsun Chiu, Yu-Ming Lin, Chih-Hao Wang
  • Drain side recess for back-side power rail device
    Patent number: 11658220
    Abstract: A semiconductor transistor device includes a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. The gate structure wraps around the channel structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are disposed on opposite endings of the channel structure. The gate contact is disposed on the gate structure. The back-side source/drain contact is disposed under the first source/drain epitaxial structure. The second source/drain epitaxial structure has a concave bottom surface.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: May 23, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang, Kuo-Cheng Chiang
  • Backside gate contact
    Patent number: 11658226
    Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Lin-Yu Huang, Lo-Heng Chang, Cheng-Chi Chuang, Chih-Hao Wang
  • AIR SPACER AND CAPPING STRUCTURES IN SEMICONDUCTOR DEVICES
    Publication number: 20230154921
    Abstract: A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.
    Type: Application
    Filed: January 23, 2023
    Publication date: May 18, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Yu Huang, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • LIVE STREAMING INTERFACE INTERACTION METHOD AND APPARATUS, ELECTRONIC DEVICE, AND COMPUTER-READABLE MEDIUM
    Publication number: 20230144560
    Abstract: The present disclosure relates to the field of network live streaming, and provides a live streaming interface interaction method and apparatus, an electronic device, and a computer-readable medium. The method comprises: displaying, on a live streaming interface, a first function control and a second function control used for indicating the same function state; receiving an interactive operation acting on the live streaming interface, and switching the function state of the first function control and the second function control when it is determined that the interactive operation meets a preset condition; and respectively displaying corresponding guide animations on display positions corresponding to the first function control and the second function control, so as to prompt a user to perform the next interactive operation.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 11, 2023
    Inventors: Wenjing LIU, Cheng CHI, Kun CHANG, Guizhang CHEN, Yu LI, Chenkang LI, Meng CHEN, Zhenwei LAI, Yingke WANG
  • INTEGRATED CIRCUIT WITH BACKSIDE TRENCH FOR NANOSHEET REMOVAL
    Publication number: 20230137307
    Abstract: An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The integrated circuit includes a backside trench through the substrate that removes a lowest semiconductor nanosheet of the first nanosheet transistor while leaving the lowest semiconductor nanosheet of the second nanosheet transistor. The backside trench is filled with a dielectric material.
    Type: Application
    Filed: March 11, 2022
    Publication date: May 4, 2023
    Inventors: Chun-Yuan CHEN, Li-Zhen YU, Huan-Chieh SU, Cheng-Chi CHUANG, Chih-Hao WANG
  • SEMICONDUCTOR DEVICE HAVING DIELECTRIC HYBRID FIN
    Publication number: 20230138012
    Abstract: A device includes a substrate and a transistor on the substrate. The transistor includes a channel region that has at least one semiconductor nanostructure, and a gate electrode. A source/drain region is disposed adjacent to a first side of the channel region along a first direction. A hybrid fin structure is disposed adjacent to a second side of the channel region along a second direction that is transverse to the first direction. The hybrid fin structure includes a first hybrid fin dielectric layer and a second hybrid fin dielectric layer. The first and second hybrid fin dielectric layers include silicon, oxygen, carbon and nitrogen and have a different concentration of at least one of silicon oxygen, carbon, or nitrogen from one another.
    Type: Application
    Filed: May 12, 2022
    Publication date: May 4, 2023
    Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Li-Zhen YU, Cheng-Chi CHUANG, Chih-Hao WANG
  • Semiconductor devices including metal gate protection and methods of fabrication thereof
    Patent number: 11640941
    Abstract: Embodiments of the present disclosure provide semiconductor device structures. In one embodiment, the semiconductor device structure includes a gate dielectric layer, a gate electrode layer in contact with the gate dielectric layer, a first self-aligned contact (SAC) layer disposed over the gate electrode layer, an isolation layer disposed between the gate electrode layer and the first SAC layer, and a first sidewall spacer in contact with the gate dielectric layer, the isolation layer, and the first SAC layer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: May 2, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Tsung Wang, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • ELECTRONIC DEVICE AND METHOD OF FABRICATING AN ELECTRONIC DEVICE
    Publication number: 20230129218
    Abstract: An electronic device including a connection element is provided. The connection element includes a first insulation layer and a second insulation layer. The first insulation layer has a first opening. A sidewall of the first insulation layer at the first opening has roughness different from roughness of a top surface of the first insulation layer. The second insulation layer is disposed on the first insulation layer, and the second insulation layer has a second opening. The sidewall of the first insulation layer at the first opening is exposed by the second opening. A method of fabricating an electronic device is also provided.
    Type: Application
    Filed: May 18, 2022
    Publication date: April 27, 2023
    Applicant: Innolux Corporation
    Inventors: Chin-Lung Ting, Ker-Yih Kao, Cheng-Chi Wang, Kuang-Ming Fan, Chun-Hung Chen, Wen-Hsiang Liao, Ming-Hsien Shih
  • Advanced metal connection with metal cut
    Patent number: 11637064
    Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shun Li Chen, Shih-Wei Peng, Tien-Lu Lin
  • Integrated circuit and method for forming the same
    Patent number: 11637066
    Abstract: An integrated circuit includes a strip structure having a front side and a back side. A gate structure is on the front side of the strip structure. The integrated circuit includes a plurality of channel layers above the front side of the strip structure, wherein each of the plurality of channel layers is enclosed within the gate structure. An isolation structure surrounds the strip structure. The integrated circuit includes a backside via in the isolation structure. An epitaxy structure is on the front side of the strip structure. The integrated circuit includes a contact over the epitaxy structure. The contact has a first portion on a first side of the epitaxy structure. The first portion of the contact extends into the isolation structure and contacts the backside via. The integrated circuit includes a backside power rail on the back side of the strip structure and contacting the backside via.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: April 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Wei-Cheng Lin, Cheng-Chi Chuang, Jiann-Tyng Tzeng
  • Source/Drain Contacts and Methods of Forming Same
    Publication number: 20230120499
    Abstract: A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Semiconductor Device and Method of Forming Thereof
    Publication number: 20230123733
    Abstract: A device includes a device layer including a first transistor, a first interconnect structure on a front-side of the device layer, and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric material on the backside of the device layer, a contact extending through the first dielectric material to a first source/drain region of the first transistor, and a first conductive layer including a first conductive line electrically connected to the first source/drain region through the contact.
    Type: Application
    Filed: December 16, 2022
    Publication date: April 20, 2023
    Inventors: Li-Zhen Yu, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su
  • NANOSHEET TRANSISTOR DEVICES WITH DIFFERENT ACTIVE CHANNEL WIDTHS
    Publication number: 20230123883
    Abstract: A semiconductor structure comprises a substrate defining a first axis and a second axis orthogonal to the first axis, a first nanosheet region disposed on the substrate and defining a first channel width along the second axis, a first gate disposed around the first nanosheet region, a second nanosheet region disposed on the substrate and defining a second channel width along the second axis less than the first channel width of the first nanosheet region and a second gate disposed around the second nanosheet region.
    Type: Application
    Filed: September 25, 2021
    Publication date: April 20, 2023
    Inventors: Ruilong Xie, Julien Frougier, Kangguo Cheng, Chanro Park, Cheng Chi, Jinning Liu
  • INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE INTERCONNECTION STRUCTURE HAVING AIR GAP
    Publication number: 20230121408
    Abstract: A method includes forming a transistor over a substrate; forming a front-side interconnection structure over the transistor; after forming the front-side interconnection structure, removing the substrate; after removing the substrate, forming a backside via to be electrically connected to the transistor; depositing a dielectric layer to cover the backside via; forming an opening in the dielectric layer to expose the backside via; forming a spacer structure on a sidewall of the opening; after forming a spacer structure, forming a conductive feature in the opening to be electrically connected to the backside via; and after forming the conductive feature, forming an air gap in the spacer structure.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 20, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang