Abstract: A grid structure in a pixel array may be at least partially angled or tapered toward a top surface of the grid structure such that the width of the grid structure approaches a near-zero width near the top surface of the grid structure. This permits the spacing between color filter regions in between the grid structure to approach a near-zero spacing near the top surfaces of the color filter regions. The tight spacing of color filter regions provided by the angled or tapered grid structure provides a greater surface area and volume for incident light collection in the color filter regions. Moreover, the width of the grid structure may increase at least partially toward a bottom surface of the grid structure such that the wider dimension of the grid structure near the bottom surface of the grid structure provides optical crosstalk protection for the pixel sensors in the pixel array.

Abstract: A multi-mode hybrid control DC-DC converting circuit has a switching power converter and a microcontroller. The switching power converter has a transformer and a switching switch. The switching switch is connected to a primary-side winding of the transformer in series. The microcontroller is connected to the switching power converter and a control terminal of the switching switch. The microcontroller sets multiple thresholds according to an input voltage of the switching power converter, and determines whether a feedback voltage of the switching power converter is higher or lower than each one of the thresholds to perform a variable-frequency mode, a constant-frequency mode, or a pulse-skipping mode. The microcontroller outputs a driving signal to the switching switch and correspondingly adjusts a frequency of the driving signal according to the variable-frequency mode, the constant-frequency mode, or the pulse-skipping mode which is performed.

Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.

Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.

Abstract: An optical device is provided. The optical device includes a ring waveguide and a bus waveguide. The ring waveguide includes a coupling region. The bus waveguide is disposed adjacent to and spaced apart from the coupling region of the ring waveguide. The bus waveguide includes a coupling structure corresponding to the coupling region.

Abstract: A display assembly including a stand, a mounting assembly and a display. The mounting assembly includes a fixed base, a first pivot, a pivotable base, a second pivot, a handle, a plurality of first engagement structures and a second engagement structure. The handle includes a handheld part and a mounting part. The mounting part is connected to the handheld part and pivotally connected to the pivotable base via the second pivot. The first engagement structures are disposed at one of the fixed base and the mounting part of the handle. The second engagement structure is disposed at another one of the fixed base and the mounting part of the handle. The display is fixed on the pivotable base. The first pivot is not coaxial with the second pivot so that the second engagement structure is configured to be engaged with any one of the first engagement structures.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a stack of semiconductor layers comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers over a semiconductor substrate. A first stack of masking layers is formed over the stack of semiconductor layers with a first width and a second stack of masking layers is formed laterally offset from the stack of semiconductor layers with a second width less than the first width. A patterning process is performed on the semiconductor substrate and the stack of semiconductor layers, thereby defining a first fin structure laterally adjacent to a second fin structure. The first fin structure has the first width and the second fin structure has the second width. The stack of semiconductor layers directly overlies the first fin structure and has the first width.

Abstract: Disclosed are an image display method and a 3d display system. The method is adapted to the 3d display system including a 3d display device and includes the following steps. A first image and a second image are obtained by splitting an input image according to a 3d image format. Whether the input image is a 3D format image complying with the 3D image format is determined through a stereo matching processing performed on the first image and the second image. An image interweaving process is enabled to be performed on the input image to generate an interweaving image in response to determining that the input image is the 3D format image complying with the 3D image format, and the interweaving image is displayed via the 3D display device.

Abstract: The present disclosure provides a semiconductor device, a photonic circuit, and a method for adjusting a resonant wavelength of an optical modulator. The semiconductor device includes a substrate, a first waveguide disposed on the substrate, and a second waveguide disposed on the substrate and spaced apart from the first waveguide with a first distance. In addition, the second waveguide includes a first electrical coupling portion having a first type doping, a second electrical coupling portion having a second type doping, and an optical coupling portion disposed between the first electrical coupling portion and the second electrical coupling portion, wherein the second waveguide is configured to receive a first voltage through the first electrical coupling portion and the second electrical coupling portion to decrease a resonant wavelength of the second waveguide.

Abstract: A dust-proof sensing device includes a mechanical body, a feeding path, a first photoelectric sensor disposed above the feeding path, a second photoelectric sensor disposed under the feeding path, and an upper bracket. The mechanical body has a feeding path. The upper bracket is mounted above the feeding path. The upper bracket has an upper fastening portion fastened to the mechanical body, an upper wedging portion fastened at the upper fastening portion, an L-shaped upper light guiding holder fastened at the upper fastening portion, and a first light guider fastened at the upper light guiding holder. The upper fastening portion has a first inclined section. An inner edge of an upper surface of the first inclined section is intersected with a top edge of an inner surface of the upper wedging portion to form a clamping angle.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: A backlit-module-embedded illuminated keyswitch structure includes a baseplate, a mask film disposed below the baseplate and having a first coating configured to substantially reflect a light, a light guide sheet disposed at one side of the mask film and having a light source hole, a reflective layer disposed at one side of the light guide sheet opposite to the mask film and having an opening communicating with the light source hole, a top glue configured to connect the mask film and the light guide sheet around the light source hole, and a bottom glue configured to connect the light guide sheet and the reflective layer around the light source hole. The first coating covers the light source hole. In a stacked direction of the mask film, the light guide sheet, and the reflective layer, at least one of the top glue and the bottom glue overlaps the first coating.

Abstract: A wavelength conversion member includes a substrate, a phosphor layer, and a ventilated blade. The substrate is configured to rotate based on an axis. The phosphor layer is disposed on the substrate. The ventilated blade is disposed on the substrate and has a pore density between 10 ppi and 500 ppi or a volume porosity between 5% and 95%.

Abstract: A smart interpreter engine is provided. The smart interpreter engine includes a speech to text converter, a natural language processing module and a translator. The speech to text converter is utilized for converting speech data corresponding to a first language into text data corresponding to the first language. The natural language processing module is utilized for converting the text data corresponding to the first language into glossary text data corresponding to the first language according to a game software. The translator is utilized for converting the glossary text data corresponding to the first language into text data corresponding to a second language.

Abstract: A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.

Abstract: A CMOS image sensor includes PDAF pixels distributed in an array of image pixels in plan view. Each PDAF pixel includes m×m binned photodiodes, a PDAF color filter overlying the binned photodiodes and laterally surrounded by a first isolation structure, and a PDAF micro-lens overlying the PDAF color filter. A first horizontal distance between a center of the PDAF color filter and a center of the binned photodiodes varies depending on a location of the PDAF pixel in plan view in the CMOS image sensor. Additionally, the first isolation structure includes a first low-n dielectric grid, a second low-n dielectric grid underlying the first low-n dielectric grid, and a metal grid enclosed by the second low-n dielectric grid. The second low-n dielectric grid includes a filler dielectric material different from a second low-n dielectric grid material. Thus, quantum efficiency and uniformity of the CMOS image sensor are improved.

Abstract: A variable aperture module includes a blade assembly, a positioning element, a driving part and pressing structures. The blade assembly includes movable blades disposed around an optical axis to form a light passable hole with an adjustable size. Each movable blade has a positioning hole and a movement hole adjacent thereto. The positioning element includes positioning structures disposed respectively corresponding to the positioning holes. The driving part includes a rotation element disposed corresponding to the movement holes and is rotatable with respect to the positioning element. The pressing structures are disposed respectively corresponding to the movable blades. Each pressing structure is at least disposed into at least one of the positioning hole and the movement hole of the corresponding movable blade. Each pressing structure at least presses against at least one of the corresponding one positioning structure and the rotation element.

Abstract: A resistive random-access memory (RRAM) circuit includes an RRAM device configured to output a cell current responsive to a bit line voltage, and a current limiter including an input terminal coupled to the RRAM device, first and second parallel current paths configured to conduct the cell current between the input terminal and a reference voltage node, and an amplifier configured to generate a first signal responsive to a voltage level at the input terminal and a reference voltage level. Each of the first and second current paths includes a switching device configured to selectively conduct a portion of the cell current responsive to the first signal.

Abstract: A self-driven active clamp circuit applied to a flyback converter having a transformer and a switch has a clamp switch and a resistor. The clamp switch is connected between a first capacitor and a second capacitor in series. Another terminal of the first capacitor is connected to a first terminal of a primary-side winding of the transformer. Another terminal of the second capacitor is connected to a second terminal of the primary-side winding of the transformer and the switch of the flyback converter. A terminal of the resistor is connected to a control terminal of the clamp switch. Another terminal of the resistor is connected to the second terminal of the primary-side winding of the transformer and the switch of the flyback converter.