Abstract: A projection device and a driving method of the projection device are provided. The projection device includes a signal processing circuit, a driving circuit, a light-emitting module, and a discharge circuit. The signal processing circuit is configured to provide a modulation signal and a first signal. The driving circuit is coupled to the signal processing circuit and a driving node. The driving circuit is configured to generate a driving signal to the driving node according to the modulation signal. The light-emitting module is coupled to the driving circuit through the driving node. The light-emitting module is configured to receive the driving signal from the driving node to accordingly emit a laser beam. The discharge circuit is coupled to the signal processing circuit and the driving node. The discharge circuit is configured to provide a reference voltage to the driving node according to the first signal.

Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.

Abstract: A memory device is provided. The memory device includes multiple first memory arrays, a first write word line driver, and multiple first read word line drivers. Each of the first read word line drivers is coupled to one array in the first memory arrays. A selected one in the first read word line drivers generates a first word line voltage to a corresponding array in the first memory arrays in a first read operation. A first write word line driver is coupled to at least two drivers in the first read word line drivers, and generates a second word line voltage to the first memory arrays in a first write operation. The second word line voltage is greater than the first word line voltage.

Abstract: A method for manufacturing a semiconductor device includes forming one or more work function layers over a semiconductor structure. The method includes forming a hardmask layer over the one or more work function layers. The method includes forming an adhesion layer over the hardmask layer. The method includes removing a first portion of a patternable layer that is disposed over the hardmask layer. The adhesion layer comprises an organic acid that concurrently bonds metal atoms of the hardmask layer and phenol groups of the patternable layer, thereby preventing an etchant from penetrating into a second portion of the patternable layer that still remains over the hardmask layer.

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

Abstract: Disclosed herein is a recombinant antibody or a fragment thereof exhibiting binding affinity and specificity toward B7-H3. According to some embodiments of the present disclosure, the recombinant antibody or its fragment comprises a heavy chain variable (VH) domain and a light chain variable (VL) domain respectively having the amino acid sequences of SEQ ID NOs: 7 and 8. Also disclosed herein are an immunoconjugate comprising the recombinant antibody or its fragment, and a method of treating cancers by use of the present immunoconjugate.

Abstract: A ratchet wrench is provided, wherein the ratchet wrench includes: a rod body including a working end and a grip; a barrel rotatably connected to the working end and including limitation teeth and a positioning portion; a driving assembly rotatably disposed within the barrel and including a driving member including a connection portion, a lid covered on an end of the barrel, a fastener connecting the driving member and the lid, and a ratchet assembly including meshing teeth meshed with the limitation teeth, the fastener being axially non-movable relative to the driving member; and a locking mechanism including a pin movably received in the rod body, a locking elastic member received in the rod body and biasing the pin to interlock with the positioning portion, and a slidable member movably inserted in the rod body and including a buckle member buckled with the pin.

Abstract: A method of an interconnect structure includes the following steps. A first etching stop layer, a first dielectric layer, a second etching stop layer, an insert layer and a second dielectric layer are deposited over the second etching stop layer are deposited over a substrate. The second dielectric layer, the insert layer, the second etching stop layer, the first dielectric layer and the first etching stop layer are patterned thereby forming a trench opening and a via hole. A conductive feature is filled in the trench opening and the via hole thereby forming a conductive line in the second dielectric layer and the insert layer and a via in the first etching stop layer and the first dielectric layer. A material of the insert layer is different from the second dielectric layer and the second etching stop layer.

Abstract: A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.

Abstract: A memory circuit includes a bias voltage generator including a first node, a current source coupled between a first power supply node and the first node, and a first transistor and a first resistive device coupled in series between the first node and a power reference node. A drive circuit includes a second node, an amplifier including a first input terminal coupled to the first node and a second input terminal coupled to the second node, and a second transistor coupled between a second power supply node and the second node and including a gate coupled to an output terminal of the amplifier, and a resistive random-access memory (RRAM) device is coupled between the second node and the power reference node.

Abstract: A system includes a charge pump system having a plurality of enable signal input terminals and an output terminal, the charge pump system configured to provide an output voltage at the output terminal; and a detection circuit connected to the enable terminals and the output terminal of the charge pump system, the detection circuit configured to compare the charge pump system output voltage to a plurality of predefined input detection voltage levels, and to selectively output a plurality of enable signals to the charge pump system enable signal input terminals in response to the comparison.

Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.

Abstract: The present invention discloses a processor control method including: controlling a processor to execute a first operating system in a first state; when the processor executing the first operating system satisfies a predetermined condition, controlling the processor to switch from the first state to a second state; and controlling the processor to execute a second operating system in the second state, wherein an authority of the first state is higher than an authority of the second state.

Abstract: A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.

Abstract: A method of operating a memory circuit includes generating, by a first memory cell array, a first current in response to a first voltage, generating, by a tracking circuit, a second set of leakage currents, generating, by a first current source, a second write current, and mirroring, by a first current mirror. The first current includes a first set of leakage currents and a first write current. The first current is in a first path with a second current in a second path. The second current includes the second set of leakage currents and the second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents. The second set of leakage currents is configured to track the first set of leakage currents of the first memory cell array.

Abstract: A semiconductor device is provided, including a substrate, a transistor structure, a metal silicide layer, and a metal silicon nitride layer. The transistor structure is formed on the substrate. The transistor structure includes a source region, a drain region and a gate structure. The gate structure is located between the source region and the drain region. The metal silicide layer is formed on the top surface of the source region and the top surface of the drain region, and the metal silicon nitride layer is formed on the surface of the metal silicide layer.

Abstract: A method of forming an interconnect structure includes the following steps. A first etching stop layer, a first dielectric layer, a second etching stop layer, an insert layer and a second dielectric layer are deposited over the second etching stop layer are deposited over a substrate. The second dielectric layer, the insert layer, the second etching stop layer, the first dielectric layer and the first etching stop layer are patterned thereby forming a trench opening and a via hole. A conductive feature is filled in the trench opening and the via hole thereby forming a conductive line in the second dielectric layer and the insert layer and a via in the first etching stop layer and the first dielectric layer. A material of the insert layer is different from the second dielectric layer and the second etching stop layer.

Abstract: A method includes forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising a plurality of sacrificial layers that alternate with a plurality of channel layers, forming a dummy gate stack over a top surface and sidewalls of the multi-layer stack, forming first spacers on sidewalls of the dummy gate stack, growing an epitaxial source/drain region that extends through the plurality of sacrificial layers and the plurality of channel layers, forming a metal-semiconductor alloy region on first portions of the epitaxial source/drain region, forming a coating layer on the metal-semiconductor alloy region, wherein during the forming of the metal-semiconductor alloy region and the coating layer, a residual layer is formed on sidewalls of the first spacers, and performing a wet clean process to selectively etch the residual layer from the sidewalls of the first spacers.

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.