Abstract: A system includes a charge pump system having a plurality of enable signal input terminals and an output terminal, the charge pump system configured to provide an output voltage at the output terminal; and a detection circuit connected to the enable terminals and the output terminal of the charge pump system, the detection circuit configured to compare the charge pump system output voltage to a plurality of predefined input detection voltage levels, and to selectively output a plurality of enable signals to the charge pump system enable signal input terminals in response to the comparison.

Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.

Abstract: The present invention discloses a processor control method including: controlling a processor to execute a first operating system in a first state; when the processor executing the first operating system satisfies a predetermined condition, controlling the processor to switch from the first state to a second state; and controlling the processor to execute a second operating system in the second state, wherein an authority of the first state is higher than an authority of the second state.

Abstract: A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.

Abstract: A method of operating a memory circuit includes generating, by a first memory cell array, a first current in response to a first voltage, generating, by a tracking circuit, a second set of leakage currents, generating, by a first current source, a second write current, and mirroring, by a first current mirror. The first current includes a first set of leakage currents and a first write current. The first current is in a first path with a second current in a second path. The second current includes the second set of leakage currents and the second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents. The second set of leakage currents is configured to track the first set of leakage currents of the first memory cell array.

Abstract: A semiconductor device is provided, including a substrate, a transistor structure, a metal silicide layer, and a metal silicon nitride layer. The transistor structure is formed on the substrate. The transistor structure includes a source region, a drain region and a gate structure. The gate structure is located between the source region and the drain region. The metal silicide layer is formed on the top surface of the source region and the top surface of the drain region, and the metal silicon nitride layer is formed on the surface of the metal silicide layer.

Abstract: A method of forming an interconnect structure includes the following steps. A first etching stop layer, a first dielectric layer, a second etching stop layer, an insert layer and a second dielectric layer are deposited over the second etching stop layer are deposited over a substrate. The second dielectric layer, the insert layer, the second etching stop layer, the first dielectric layer and the first etching stop layer are patterned thereby forming a trench opening and a via hole. A conductive feature is filled in the trench opening and the via hole thereby forming a conductive line in the second dielectric layer and the insert layer and a via in the first etching stop layer and the first dielectric layer. A material of the insert layer is different from the second dielectric layer and the second etching stop layer.

Abstract: A method includes forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising a plurality of sacrificial layers that alternate with a plurality of channel layers, forming a dummy gate stack over a top surface and sidewalls of the multi-layer stack, forming first spacers on sidewalls of the dummy gate stack, growing an epitaxial source/drain region that extends through the plurality of sacrificial layers and the plurality of channel layers, forming a metal-semiconductor alloy region on first portions of the epitaxial source/drain region, forming a coating layer on the metal-semiconductor alloy region, wherein during the forming of the metal-semiconductor alloy region and the coating layer, a residual layer is formed on sidewalls of the first spacers, and performing a wet clean process to selectively etch the residual layer from the sidewalls of the first spacers.

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

Abstract: A memory circuit includes a first driver circuit, a memory cell array including a first column of memory cells, a first transistor coupled between the first driver circuit and the memory cell array, a second driver circuit, a first column of tracking cells and a header circuit coupled to the first driver circuit and the second driver circuit. The first transistor is configured to receive a first select signal. The first column of tracking cells is configured to track a leakage current of the first column of memory cells, and is coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit.

Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.

Abstract: A system includes a charge pump system having a plurality of enable signal input terminals and an output terminal, the charge pump system configured to provide an output voltage at the output terminal; and a detection circuit connected to the enable terminals and the output terminal of the charge pump system, the detection circuit configured to compare the charge pump system output voltage to a plurality of predefined input detection voltage levels, and to selectively output a plurality of enable signals to the charge pump system enable signal input terminals in response to the comparison.

Abstract: An anti-PD-L1 antibody, or an antigen-binding fragment thereof, comprising: a heavy chain variable region comprising the three CDRs with the sequences of SEQ ID NOs: 2-4, 6-8, 10-12, 14-16, or 18-20; and/or a light chain variable region comprising the three CDRs with the sequences of SEQ ID NOs: 22-24, 26-28, 30-32, 34-36, or 38-40, wherein the antibody is a chimeric, humanized, composite, or human antibody.

Abstract: A method is provided for processing wastewater having organics even together with high-concentration ammonia-nitrogen, using an apparatus, comprising a catalyzation tank and a subsequent neutralization tank. Organic ammonia-nitrogen wastewater is introduced into tank for reaction without being pre-adjusted by acidic agent or mixing with other additives. A persulfate oxidant is used to process high-efficiency oxidative degradation for ammonia-nitrogen and toxic organics in wastewater through catalyzing oxidation of ultraviolet activation, tiny-amount-transition-metal catalyzation, or both of them, for simultaneous reductions or complete removals of ammonia-nitrogen and organic carbon contents. After neutralization according to actual needs, the final output is complied with biological treatment conditions, discharged-water quality standards, or recycled-water standards.

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

Abstract: A fabrication method includes: forming, above a substrate, a first electrode having a varying density that increases from a first density level at a bottom surface of the first electrode to a second density level that is higher than the first density level at a top surface of the first electrode; forming a high-K dielectric layer over the first electrode; and forming a second electrode over the HK dielectric layer having a varying density that increases from a third density level at a bottom surface of the second electrode that bonds to the HK dielectric layer to a fourth density level that is higher than the third density level at a top surface of the second electrode.

Abstract: A circuit includes a memory macro comprising a plurality of memory banks. The circuit includes a first voltage regulator configured to provide a first operation voltage to the memory macro at a first output node. The circuit includes a second voltage regulator configured to provide a second operation voltage to the memory macro at a second output node. The second operation voltage is substantially higher than the first operation voltage. The circuit includes a decoupling capacitor configured to be alternately shared by the first voltage regulator when the memory macro receives the first operation voltage, and by the second voltage regulator when the memory macro receives the second operation voltage.

Abstract: A memory device includes a first memory array including a plurality of first memory bits. Each of the plurality of first memory bits is configured as a one-time-programmable (OTP) memory bit. A second memory array includes a plurality of second memory bits, each of the plurality of second memory bits being configured as a multi-time-programmable (MTP) memory bit. A lock bit circuit operatively coupled to the first memory array and not the second memory array. The lock bit circuit is configured to generate a lock bit indicative of whether at least one of the plurality of first memory bits has been programmed.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first electrode layer over a substrate. The method includes forming a capacitor dielectric layer over the first electrode layer and the substrate. The method includes depositing a second electrode layer over the capacitor dielectric layer. The method includes bombarding the second electrode layer with ions of an inert gas to sputter first atoms from the second electrode layer. The treated second electrode layer has a treated first top portion, a treated first sidewall portion, and a treated first bottom portion. The treated first sidewall portion is over the sidewall of the first electrode layer and connected between the treated first top portion and the treated first bottom portion, and the treated first sidewall portion is thicker than the first sidewall portion.

Abstract: A projection device and a driving method of the projection device are provided. The projection device includes a signal processing circuit, a driving circuit, a light-emitting module, and a discharge circuit. The signal processing circuit is configured to provide a modulation signal and a first signal. The driving circuit is coupled to the signal processing circuit and a driving node. The driving circuit is configured to generate a driving signal to the driving node according to the modulation signal. The light-emitting module is coupled to the driving circuit through the driving node. The light-emitting module is configured to receive the driving signal from the driving node to accordingly emit a laser beam. The discharge circuit is coupled to the signal processing circuit and the driving node. The discharge circuit is configured to provide a reference voltage to the driving node according to the first signal.