Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.

Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.

Abstract: A display assembly including a stand, a mounting assembly and a display. The mounting assembly includes a fixed base, a first pivot, a pivotable base, a second pivot, a handle, a plurality of first engagement structures and a second engagement structure. The handle includes a handheld part and a mounting part. The mounting part is connected to the handheld part and pivotally connected to the pivotable base via the second pivot. The first engagement structures are disposed at one of the fixed base and the mounting part of the handle. The second engagement structure is disposed at another one of the fixed base and the mounting part of the handle. The display is fixed on the pivotable base. The first pivot is not coaxial with the second pivot so that the second engagement structure is configured to be engaged with any one of the first engagement structures.

Abstract: The present invention discloses a processor control method including: controlling a processor to execute a first operating system in a first state; when the processor executing the first operating system satisfies a predetermined condition, controlling the processor to switch from the first state to a second state; and controlling the processor to execute a second operating system in the second state, wherein an authority of the first state is higher than an authority of the second state.

Abstract: A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.

Abstract: A resistive random-access memory (RRAM) circuit includes an RRAM device configured to output a cell current responsive to a bit line voltage, and a current limiter including an input terminal coupled to the RRAM device, first and second parallel current paths configured to conduct the cell current between the input terminal and a reference voltage node, and an amplifier configured to generate a first signal responsive to a voltage level at the input terminal and a reference voltage level. Each of the first and second current paths includes a switching device configured to selectively conduct a portion of the cell current responsive to the first signal.

Abstract: A self-driven active clamp circuit applied to a flyback converter having a transformer and a switch has a clamp switch and a resistor. The clamp switch is connected between a first capacitor and a second capacitor in series. Another terminal of the first capacitor is connected to a first terminal of a primary-side winding of the transformer. Another terminal of the second capacitor is connected to a second terminal of the primary-side winding of the transformer and the switch of the flyback converter. A terminal of the resistor is connected to a control terminal of the clamp switch. Another terminal of the resistor is connected to the second terminal of the primary-side winding of the transformer and the switch of the flyback converter.

Abstract: A structure includes a first conductive feature, a first etch stop layer over the first conductive feature, a dielectric layer over the first etch stop layer, and a second conductive feature in the dielectric layer and the first etch stop layer. The second conductive feature is over and contacting the first conductive feature. An air spacer encircles the second conductive feature, and sidewalls of the second conductive feature are exposed to the air spacer. A protection ring further encircles the second conductive feature, and the protection ring fully separates the second conductive feature from the air spacer.

Abstract: A semiconductor device including a substrate, a low-k dielectric layer, a cap layer, and a conductive layer is provided. The low-k dielectric layer is disposed over the substrate. The cap layer is disposed on the low-k dielectric layer, wherein a carbon atom content of the cap layer is greater than a carbon atom content of the low-k dielectric layer. The conductive layer is disposed in the cap layer and the low-k dielectric layer.

Abstract: An interconnect structure includes an etching stop layer, a dielectric layer and an insert layer and a conductive line. The insert layer is located between the etching stop layer and the dielectric layer. The conductive line extends through the dielectric layer, the insert layer, and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer.

Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.

Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell.

Abstract: A yellow light emitting device may have a light source and a color converter wherein at most 1% of the total emitted radiant power of the yellow light emitting device is emitted in a wavelength range shorter than 520 nm, as well as the use of the yellow light emitting device.

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

Abstract: An optical biometer including a light source, a first-stage coupler, a first and a second second-stage coupler, a first and a second optical path difference generator, a first and a second optical component set, a first and a second detection device is disclosed. The first-stage coupler receives an incident light from the light source and emits first and second first-stage lights. The first second-stage coupler receives the first first-stage light and emits first and second second-stage lights. The second second-stage coupler receives the second first-stage light and emits third and fourth second-stage lights. The first/second optical path difference generator generates the first/fourth second-stage light with the first/second optical path difference. The first/second optical component set emits the second/third second-stage light to a first/second position of an eye and receives a first/second reflected light. The first/second detector receives a first/second detection light.

Abstract: A method of an interconnect structure includes the following steps. A first etching stop layer, a first dielectric layer, a second etching stop layer, an insert layer and a second dielectric layer are deposited over the second etching stop layer are deposited over a substrate. The second dielectric layer, the insert layer, the second etching stop layer, the first dielectric layer and the first etching stop layer are patterned thereby forming a trench opening and a via hole. A conductive feature is filled in the trench opening and the via hole thereby forming a conductive line in the second dielectric layer and the insert layer and a via in the first etching stop layer and the first dielectric layer. A material of the insert layer is different from the second dielectric layer and the second etching stop layer.

Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.

Abstract: A method for treating a waste liquid comprises: step (A), adding a precursory oxidant to a waste liquid having a temperature of 25-70° C.; wherein, the precursory oxidant is hydrogen peroxide or sodium percarbonate, and in mg/L, a ratio of the precursory oxidant/the total amount of sulfide is 2.20 to 6.37; step (B), mixing an advanced oxidant and the waste liquid after step (A); wherein, the advanced oxidant is sodium persulfate or potassium persulfate, and in mg/L, a ratio of the advanced oxidant/COD after step (A) is 7.63 to 33.27; step (C), using UV illumination method to illuminate the oxidant dissolved in the waste liquid after step (B), and aerated with oxygen-containing gas. By the above-described method, it can achieve the purpose of sulfide conversion and degradation and removal of organic pollution composition under the condition free of the generation of H2S.