Patents by Inventor Cheng-Chou Hung

Cheng-Chou Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10170435
    Abstract: A method for forming a seal ring structure provides a semiconductor substrate having a first doping region formed over a top portion thereof. The method forms a plurality of patterned photoresist layers over the semiconductor substrate, encircling the semiconductor substrate, wherein each of the patterned photoresist layers has a plurality of parallel strip portions extending along a first direction and a plurality of bridge portions formed between the parallel strip portions, and then performs an etching process to a first doping region of the substrate. The method then removes the first doping region not covered by the patterned photoresist layers and forms a plurality of patterned first doping regions. The method then removes the patterned photoresist layers and forms an isolation region between and adjacent to the patterned first doping regions. Finally, the method forms a plurality of interconnect elements over the semiconductor substrate.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 1, 2019
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Chiyuan Lu, Chien-Chih Lin, Cheng-Chou Hung, Yu-Hua Huang
  • Patent number: 10090375
    Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A conductive structure is disposed on the conductive pad, and a passive device is also disposed on the conductive pad, wherein the passive device has a first portion located above the second passivation layer and a second portion passing through the second passivation layer. A solderability preservative film covers the first portion of the passive device, and an under bump metallurgy (UBM) layer covers the second portion of the passive device and a portion of the conductive structure.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: October 2, 2018
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Cheng-Chou Hung
  • Publication number: 20180190597
    Abstract: A method for forming a seal ring structure provides a semiconductor substrate having a first doping region formed over a top portion thereof. The method forms a plurality of patterned photoresist layers over the semiconductor substrate, encircling the semiconductor substrate, wherein each of the patterned photoresist layers has a plurality of parallel strip portions extending along a first direction and a plurality of bridge portions formed between the parallel strip portions, and then performs an etching process to a first doping region of the substrate. The method then removes the first doping region not covered by the patterned photoresist layers and forms a plurality of patterned first doping regions. The method then removes the patterned photoresist layers and forms an isolation region between and adjacent to the patterned first doping regions. Finally, the method forms a plurality of interconnect elements over the semiconductor substrate.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 5, 2018
    Inventors: Chiyuan LU, Chien-Chih LIN, Cheng-Chou HUNG, Yu-Hua HUANG
  • Patent number: 9947624
    Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. The assembly further includes a second semiconductor die mounted on the first semiconductor package, having a ground pad thereon. One of the TSV interconnects of the first semiconductor package has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: April 17, 2018
    Assignee: MediaTek Inc.
    Inventors: Ming-Tzong Yang, Cheng-Chou Hung, Wei-Che Huang, Yu-Hua Huang, Tzu-Hung Lin, Kuei-Ti Chan, Ruey-Beei Wu, Kai-Bin Wu
  • Patent number: 9947627
    Abstract: A guard ring structure having a semiconductor substrate with a circuit region encircled by a first ring and a second ring. At least one of the first and second ring includes: a plurality of separated doping regions formed in various top portions of the semiconductor substrate, providing P-N junction or N-P junction on bottom of the plurality of separated doping regions; and an interconnect element formed over the semiconductor substrate, covering at least portion of the plurality of separated doping regions.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: April 17, 2018
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Chiyuan Lu, Chien-Chih Lin, Cheng-Chou Hung, Yu-Hua Huang
  • Patent number: 9899261
    Abstract: A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect structure formed in the substrate, and a first guard ring doped region and a second guard ring doped region formed in the substrate. The second guard ring doped region is disposed between the first guard ring doped region and the TSV interconnect structure.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: February 20, 2018
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Chou Hung, Ming-Tzong Yang, Tung-Hsing Lee, Wei-Che Huang, Yu-Hua Huang, Tzu-Hung Lin
  • Patent number: 9859356
    Abstract: A semiconductor integrated circuit includes an inductor and a plurality of high permeability patterns. The inductor includes one conductive loop. The high permeability patterns are disposed adjacent to the conductive loop.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: January 2, 2018
    Assignee: MediaTek, Inc.
    Inventors: Ming-Da Tsai, Tao-Yi Lee, Cheng-Chou Hung, Tung-Hsing Lee
  • Patent number: 9806146
    Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; a first doped region of type one, doped in the well of type two; and a second doped region of type two, provided in the well of type one and the well of type two, not touching the first doped region of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: October 31, 2017
    Assignee: MEDIATEK INC.
    Inventors: Bo-Shih Huang, Chien-Hui Chuang, Cheng-Chou Hung
  • Patent number: 9786560
    Abstract: A method for forming a semiconductor package structure is provided. The method for forming a semiconductor package structure includes providing a substrate, wherein the substrate has a front side and a back side, forming a first guard ring doped region and a second guard ring doped region in the substrate, wherein the first guard ring doped region and the second guard ring doped region have different conductive types, forming a trench through the substrate from a back side of the substrate, conformally forming an insulating layer lining the back side of the substrate, a bottom surface and sidewalls of the trench, removing a portion of the insulating layer on the back side of the substrate to form a through via, and forming a conductive material in the through via, wherein a through silicon via (TSV) interconnect structure is formed by the insulating layer and the conductive material.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: October 10, 2017
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Chou Hung, Ming-Tzong Yang, Tung-Hsing Lee, Wei-Che Huang, Yu-Hua Huang, Tzu-Hung Lin
  • Patent number: 9712130
    Abstract: An implementation of the invention is directed to a passive device cell having a substrate layer, and intermediary layer formed above the substrate layer, and a passive device formed above the intermediary layer. The intermediary layer includes a plurality of LC resonators and a plurality of segmented conductive lines, wherein the plurality of segmented conductive lines are disposed between the plurality of LC resonators.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: July 18, 2017
    Assignee: MEDIATEK INC.
    Inventors: Ming-Tzong Yang, Cheng-Chou Hung, Tung-Hsing Lee, Wei-Che Huang
  • Publication number: 20170179055
    Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A conductive structure is disposed on the conductive pad, and a passive device is also disposed on the conductive pad, wherein the passive device has a first portion located above the second passivation layer and a second portion passing through the second passivation layer. A solderability preservative film covers the first portion of the passive device, and an under bump metallurgy (UBM) layer covers the second portion of the passive device and a portion of the conductive structure.
    Type: Application
    Filed: March 6, 2017
    Publication date: June 22, 2017
    Inventors: Tzu-Hung LIN, Cheng-Chou HUNG
  • Patent number: 9640489
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. And, a plurality of doping regions are located beneath the first seal ring structure.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: May 2, 2017
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Chou Hung, Tung-Hsing Lee, Yu-Hua Huang, Ming-Tzong Yang
  • Publication number: 20170110406
    Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. The assembly further includes a second semiconductor die mounted on the first semiconductor package, having a ground pad thereon. One of the TSV interconnects of the first semiconductor package has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 20, 2017
    Inventors: Ming-Tzong YANG, Cheng-Chou HUNG, Wei-Che HUANG, Yu-Hua HUANG, Tzu-Hung LIN, Kuei-Ti CHAN, Ruey-Beei WU, Kai-Bin WU
  • Patent number: 9620580
    Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A passive device is disposed on the conductive pad, passing through the second passivation layer. An organic solderability preservative film covers the passive device.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: April 11, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Cheng-Chou Hung
  • Patent number: 9620640
    Abstract: The invention provides a body-contact metal-oxide-semiconductor field effect transistor (MOSFET) device. The body-contact MOSFET device includes a substrate. An active region is disposed on the substrate. A gate strip is extended along a first direction disposed on a first portion of the active region. A source doped region and a drain doped region are disposed on a second portion and a third portion of the active region, adjacent to opposite sides of the gate strip. The opposite sides of the gate strip are extended along the first direction. A body-contact doped region is disposed on a fourth portion of the active region. The body-contact doped region is separated from the gate strip by a fifth portion of the active region. The fifth portion is not covered by any silicide features.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: April 11, 2017
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Chou Hung, Tung-Hsing Lee, Bernard Mark Tenbroek, Rong-Tang Chen
  • Patent number: 9607894
    Abstract: An electronic device package has a base and an electronic device chip mounted on the base. The electronic device chip includes a semiconductor substrate having a front side and a back side, a electronic component disposed on the front side of the semiconductor substrate, an interconnect structure disposed on the electronic component, a through hole formed through the semiconductor substrate from the back side of the semiconductor substrate, connecting to the interconnect structure, and a TSV structure disposed in the through hole. The interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: March 28, 2017
    Assignee: MEDIATEK INC.
    Inventors: Ming-Tzong Yang, Cheng-Chou Hung, Tung-Hsing Lee, Wei-Che Huang, Yu-Hua Huang
  • Publication number: 20170084488
    Abstract: A method for forming a semiconductor package structure is provided. The method for forming a semiconductor package structure includes providing a substrate, wherein the substrate has a front side and a back side, forming a first guard ring doped region and a second guard ring doped region in the substrate, wherein the first guard ring doped region and the second guard ring doped region have different conductive types, forming a trench through the substrate from a back side of the substrate, conformally forming an insulating layer lining the back side of the substrate, a bottom surface and sidewalls of the trench, removing a portion of the insulating layer on the back side of the substrate to form a through via, and forming a conductive material in the through via, wherein a through silicon via (TSV) interconnect structure is formed by the insulating layer and the conductive material.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: Cheng-Chou HUNG, Ming-Tzong YANG, Tung-Hsing LEE, Wei-Che HUANG, Yu-Hua HUANG, Tzu-Hung LIN
  • Publication number: 20170084525
    Abstract: A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect structure formed in the substrate, and a first guard ring doped region and a second guard ring doped region formed in the substrate. The second guard ring doped region is disposed between the first guard ring doped region and the TSV interconnect structure.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: Cheng-Chou HUNG, Ming-Tzong YANG, Tung-Hsing LEE, Wei-Che HUANG, Yu-Hua HUANG, Tzu-Hung LIN
  • Publication number: 20170084685
    Abstract: A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; a first doped region of type one, doped in the well of type two; and a second doped region of type two, provided in the well of type one and the well of type two, not touching the first doped region of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.
    Type: Application
    Filed: December 1, 2016
    Publication date: March 23, 2017
    Inventors: Bo-Shih Huang, Chien-Hui Chuang, Cheng-Chou Hung
  • Patent number: 9570399
    Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor die mounted on a base. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. A first ground TSV interconnect is disposed within the interval region. A second semiconductor die is mounted on the first semiconductor die, having a ground pad thereon. The first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: February 14, 2017
    Assignee: MediaTek Inc.
    Inventors: Ming-Tzong Yang, Cheng-Chou Hung, Wei-Che Huang, Yu-Hua Huang, Tzu-Hung Lin, Kuei-Ti Chan, Ruey-Beei Wu, Kai-Bin Wu