Patents by Inventor Cheng-Chou Hung
Cheng-Chou Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8810001Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate of a conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. A capacitor is disposed under the seal ring structure and is electrically connected thereto, wherein the capacitor includes a body of the semiconductor substrate.Type: GrantFiled: January 16, 2012Date of Patent: August 19, 2014Assignee: Mediatek Inc.Inventors: Cheng-Chou Hung, Tung-Hsing Lee, Yu-Hua Huang, Ming-Tzong Yang
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Patent number: 8796813Abstract: A method for controlling an electrical property of a passive device during a fabrication of an integrated component includes providing a substrate, manufacturing the passive device on the substrate, measuring the electrical property of the passive device to obtain a measuring result, determining at least one layout pattern corresponding to at least one later manufacturing process by the measuring result for adjusting the electrical property of the passive device, and continuing the rest of the fabrication including the at least one later manufacturing process of the integrated component.Type: GrantFiled: March 12, 2013Date of Patent: August 5, 2014Assignee: MediaTek Inc.Inventors: Ming-Da Tsai, George Chien, Cheng-Chou Hung
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Publication number: 20140070346Abstract: The invention provides a radio-frequency (RF) device package and a method for fabricating the same. An exemplary embodiment of a radio-frequency (RF) device package includes a base, wherein a radio-frequency (RF) device chip is mounted on the base. The RF device chip includes a semiconductor substrate having a front side and a back side. A radio-frequency (RF) component is disposed on the front side of the semiconductor substrate. An interconnect structure is disposed on the RF component, wherein the interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure. A through hole is formed through the semiconductor substrate from the back side of the semiconductor substrate, and is connected to the interconnect structure. A TSV structure is disposed in the through hole.Type: ApplicationFiled: March 8, 2013Publication date: March 13, 2014Applicant: MEDIATEK INC.Inventors: Ming-Tzong YANG, Cheng-Chou HUNG, Tung-Hsing LEE, Wei-Che HUANG, Yu-Hua HUANG
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Publication number: 20140070416Abstract: A guard ring structure is provided, including a semiconductor substrate with a circuit region encircled by a first ring and a second ring. In one embodiment, the semiconductor substrate has a first dopant type, and the first and second ring respectively includes a plurality of separated first doping regions formed in a top portion of the semiconductor substrate, having a second dopant type opposite to the first conductivity type, and an interconnect element formed over the semiconductor substrate, covering the first doping regions.Type: ApplicationFiled: September 6, 2013Publication date: March 13, 2014Inventors: Chiyuan LU, Chien-Chih LIN, Cheng-Chou HUNG, Yu-Hua HUANG
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Publication number: 20140035096Abstract: A method for controlling an electrical property of a passive device during a fabrication of an integrated component includes providing a substrate, manufacturing the passive device on the substrate, measuring the electrical property of the passive device to obtain a measuring result, determining at least one layout pattern corresponding to at least one later manufacturing process by the measuring result for adjusting the electrical property of the passive device, and continuing the rest of the fabrication including the at least one later manufacturing process of the integrated component.Type: ApplicationFiled: March 12, 2013Publication date: February 6, 2014Applicant: MEDIATEK INC.Inventors: Ming-Da Tsai, George Chien, Cheng-Chou Hung
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Publication number: 20130265121Abstract: An embodiment of the invention provides a passive device cell. The passive device cell has a substrate layer, a passive device, and an intermediary layer formed between the substrate layer and the passive device. The intermediary layer includes a plurality of LC resonators.Type: ApplicationFiled: March 14, 2013Publication date: October 10, 2013Applicant: MediaTek Inc.Inventors: Ming-Tzong YANG, Cheng-Chou Hung, Tung-Hsing Lee, Wei-Che Huang
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Publication number: 20130264676Abstract: The invention provides a semiconductor package with a through silicon via (TSV) interconnect and a method for fabricating the same. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate. A through hole is formed through the semiconductor substrate. A TSV interconnect is disposed in a through hole. A conductive layer lines a sidewall of the through hole, surrounding the TSV interconnect.Type: ApplicationFiled: March 18, 2013Publication date: October 10, 2013Applicant: MEDIATEK INC.Inventors: Ming-Tzong YANG, Cheng-Chou HUNG, Yu-Hua HUANG, Wei-Che HUANG
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Patent number: 8507987Abstract: A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type.Type: GrantFiled: September 21, 2009Date of Patent: August 13, 2013Assignee: United Microelectronics Corp.Inventors: Sheng-Yi Huang, Cheng-Chou Hung, Tzung-Lin Li, Chin-Lan Tseng, Victor-Chiang Liang, Chih-Yu Tseng
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Patent number: 8357988Abstract: A die seal ring disposed outside of a die region of a semiconductor substrate is disclosed. The die seal ring includes a first isolation structure, a second isolation structure, and at least one third isolation structure disposed between the first isolation structure and the second isolation structure; a plurality of first regions between the first isolation structure, the second isolation structure and the third isolation structure; a second region under the first region and the third isolation structure; and a third region under the first isolation structure.Type: GrantFiled: February 6, 2009Date of Patent: January 22, 2013Assignee: United Microelectronics Corp.Inventors: Cheng-Chou Hung, Victor-Chiang Liang, Jui-Meng Jao, Cheng-Hung Li, Sheng-Yi Huang, Tzung-Lin Li, Huai-Wen Zhang, Chih-Yu Tseng
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Publication number: 20130009741Abstract: The invention provides an integrated circuit transformer disposed on a substrate. The integrated circuit transformer includes a first coiled metal pattern disposed on the substrate, comprising an inner loop segment and an outer loop segment. A second coiled metal pattern is disposed on the substrate, laterally between the inner loop segment and the outer loop segment. A dielectric layer is disposed on the first coiled metal pattern and the second coiled metal pattern. A first via is formed through the dielectric layer, electrically connecting to one of the first and second coiled metal patterns. A first redistribution pattern is disposed on the dielectric layer, electrically connecting to and extending along the first via, wherein the first redistribution pattern covers at least a portion of the first coiled metal pattern and at least a portion of the second coiled metal pattern.Type: ApplicationFiled: May 17, 2012Publication date: January 10, 2013Applicant: MEDIATEK INC.Inventors: Cheng-Chou HUNG, Cheng-Jyi CHANG, Tung-Hsing LEE, Wei-Che HUANG
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Publication number: 20120313217Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate of a conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. A capacitor is disposed under the seal ring structure and is electrically connected thereto, wherein the capacitor includes a body of the semiconductor substrate.Type: ApplicationFiled: January 16, 2012Publication date: December 13, 2012Applicant: MEDIATEK INC.Inventors: Cheng-Chou HUNG, Tung-Hsing LEE, Yu-Hua HUANG, Ming-Tzong YANG
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Publication number: 20110068415Abstract: A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type.Type: ApplicationFiled: September 21, 2009Publication date: March 24, 2011Inventors: Sheng-Yi Huang, Cheng-Chou Hung, Tzung-Lin Li, Chin-Lan Tseng, Victor-Chiang Liang, Chih-Yu Tseng
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Publication number: 20100200947Abstract: A die seal ring disposed outside of a die region of a semiconductor substrate is disclosed. The die seal ring includes a first isolation structure, a second isolation structure, and at least one third isolation structure disposed between the first isolation structure and the second isolation structure; a plurality of first regions between the first isolation structure, the second isolation structure and the third isolation structure; a second region under the first region and the third isolation structure; and a third region under the first isolation structure.Type: ApplicationFiled: February 6, 2009Publication date: August 12, 2010Inventors: Cheng-Chou Hung, Victor-Chiang Liang, Jui-Meng Jao, Cheng-Hung Li, Sheng-Yi Huang, Tzung-Lin Li, Huai-Wen Zhang, Chih-Yu Tseng
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Publication number: 20100109080Abstract: A pseudo-drain MOS transistor is disclosed. The transistor includes a semiconductor substrate; a gate structure disposed on the semiconductor substrate; a source, a pseudo-drain, a drain, and a shallow trench isolation disposed in the semiconductor substrate, a p-well disposed in the semiconductor substrate and under the source and the gate structure; and an n-well disposed under the drain. The source and the pseudo-drain are disposed adjacent to two sides of the gate structure and the shallow trench isolation is disposed between the pseudo-drain and the drain, and the n-well is extended toward the pseudo-drain while not reaching the area below the gate structure.Type: ApplicationFiled: November 5, 2008Publication date: May 6, 2010Inventors: Sheng-Yi Huang, Cheng-Chou Hung, Tzung-Lin Li, Chin-Lan Tseng, Victor-Chiang Liang, Chih-Yu Tseng
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Patent number: 7705428Abstract: A varactor on a substrate is provided. The varactor comprises a bottom electrode, an upper electrode, a first dielectric layer and a conductive layer. The bottom electrode has several doped regions arranged in the substrate as an array with several rows and several columns, wherein the doped regions in adjacent columns are arranged alternatively. The upper electrode is located over the substrate and the upper electrode is composed of several electrode locations and has several openings, wherein each opening exposes the corresponding doped region. Furthermore, each electrode location is surrounded by three doped regions. The first dielectric layer is located between the substrate and the upper electrode. The conductive layer is located over the upper electrode, wherein the conductive layer and the upper electrode are isolated from each other and the conductive layer and the doped regions are electrically connected to each other.Type: GrantFiled: March 21, 2006Date of Patent: April 27, 2010Assignee: United Microelectronics Corp.Inventors: Cheng-Chou Hung, Hua-Chou Tseng
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Publication number: 20080251863Abstract: A high-voltage RF power device includes a plurality of serially connected transistors. Each transistor includes a gate finger disposed on a substrate, a gate dielectric layer, a drain structure disposed on one side of the gate finger, and an N+ source region on the other side of the gate finger. The drain structure includes an N+ doping region encompassed by a shallow trench isolation (STI) structure, and an N well directly underneath the STI structure and the N+ doping region.Type: ApplicationFiled: April 14, 2007Publication date: October 16, 2008Inventors: Sheng-Yi Huang, Cheng-Chou Hung, Yu-Chia Chen, Chin-Lan Tseng, Chih-Yuh Tzeng, Victor-Chiang Liang, Chun-Yi Lin
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Patent number: 7367113Abstract: A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.Type: GrantFiled: April 6, 2006Date of Patent: May 6, 2008Assignee: United Microelectronics Corp.Inventors: Cheng-Chou Hung, Hua-Chou Tseng, Victor-Chiang Liang, Yu-Chia Chen, Tsun-Lai Hsu
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Publication number: 20080029854Abstract: The invention is directed to a conductive shielding pattern for shielding a inductor device. The conductive shielding pattern comprises a plurality of conductive layers and a plurality of diffusion regions. The conductive layers are located on a substrate. The diffusion regions are located in the substrate and the conductive layers and the diffusion regions are arranged alternatively and are free ends respectively.Type: ApplicationFiled: August 3, 2006Publication date: February 7, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Chou Hung, Hua-Chou Tseng, Yu-Chia Chen, Victor-Chiang Liang, Cheng-Wen Fan
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Patent number: 7321285Abstract: A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.Type: GrantFiled: April 17, 2007Date of Patent: January 22, 2008Assignee: United Microelectronics Corp.Inventors: Cheng-Chou Hung, Hua-Chou Tseng, Victor-Chiang Liang, Yu-Chia Chen, Tsun-Lai Hsu
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Publication number: 20070246801Abstract: A varactor on a substrate is provided. The varactor comprises a bottom electrode, an upper electrode, a first dielectric layer and a conductive layer. The bottom electrode has several doped regions arranged in the substrate as an array with several rows and several columns, wherein the doped regions in adjacent columns are arranged alternatively. The upper electrode is located over the substrate and the upper electrode is composed of several electrode locations and has several openings, wherein each opening exposes the corresponding doped region. Furthermore, each electrode location is surrounded by three doped regions. The first dielectric layer is located between the substrate and the upper electrode. The conductive layer is located over the upper electrode, wherein the conductive layer and the upper electrode are isolated from each other and the conductive layer and the doped regions are electrically connected to each other.Type: ApplicationFiled: March 21, 2006Publication date: October 25, 2007Inventors: Cheng-Chou Hung, Hua-Chou Tseng