Abstract: An auxiliary power supply circuit operating within a wide input voltage range has a voltage follower unit and a voltage comparison unit. The voltage follower unit has an electronic switch, a resistor, and a Zener diode. The electronic switch has a first terminal electrically connected to a voltage input terminal of the working voltage conversion circuit, a second terminal electrically connected to a voltage output terminal of the working voltage conversion circuit, and a control terminal. The resistor is electrically connected between the first terminal and the control terminal of the electronic switch. The Zener diode has a cathode electrically connected to the control terminal of the electronic switch. The voltage comparison unit has a detecting terminal electrically connected to the voltage input terminal of the working voltage conversion circuit, and an output terminal electrically connected to the control terminal of the electronic switch.

Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

Abstract: A projection device, a light source system and a projection method thereof are provided. A portion of the light-emitting units are controlled to provide a light beam as the first light beam. It is detected whether characteristic parameters of the light-emitting units providing the light beam reach a preset value. When the preset value is not reached, the light-emitting units providing the light beam are disabled, and the remaining light-emitting units are controlled to provide the back-up light beam as the first light beam. A portion of the first light beam is converted into a second light beam. The first light beam of which the wavelength is not converted and the second light beam are combined to generate an illumination beam. The illumination beam is converted into an image beam. The image beam is converted into a projection beam.

Abstract: Systems, methods, architectures, and computer program products for linking multiple devices are disclosed. In an example for linking a mobile device with a desktop device, an identifier of a mobile device can be received from a desktop computer. The identifier can be used to send a link to the mobile device. When the link is accessed, a code and a channel are generated. The mobile device is connected to the channel and the code is provided to the mobile device. The code is entered at the desktop device and the desktop device is connected to the channel responsive to the code being validated, thereby linking the desktop and mobile devices.

Abstract: An interconnect structure includes an interconnect structure includes an etching stop layer; a dielectric layer and an insert layer on the etching stop layer, and a conductive feature in the dielectric layer, the insert layer and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer.

Abstract: A wavelength conversion module and a projection device are provided. The wavelength conversion module includes a rotating member and a light sensing element. The rotating member includes a shaft and a positioning structure. An excitation beam forms a first spot on the rotating member. The shaft is located at the center of the rotating member. The positioning structure is located on the rotating member. The light sensing element is disposed adjacent to the rotating member for emitting a sensing beam toward a first surface of the rotating member, wherein the sensing beam forms a second spot on the rotating member. A first connecting line is formed by connecting the first spot and the shaft, a second connecting line is formed by connecting the second spot and the shaft, and an angle between the first connecting line and the second connecting line is greater than 30 degrees.

Abstract: A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.

Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.

Abstract: The present invention seeks to provide a method of analyzing medical image, the method comprises receiving a medical image; applying a model stored in a memory; analyzing the medical image based on the model; determining the medical image including a presence of fracture; and, transmitting an indication indicative of the determination.

Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.

Abstract: A method of forming a filament in a resistive random-access memory (RRAM) device includes applying a cell voltage across a resistive layer of the RRAM device, detecting an increase in a current through the resistive layer generated in response to the applied cell voltage, and in response to detecting the increase in the current, using a first switching device to reduce the current through the resistive layer.

Abstract: A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.

Abstract: An infrared control device is configured for use in a mesh network environment to control a controlled device by transmitting an infrared signal. The controlled device includes an identification tag. The identification tag includes a first control instruction. The control device includes a tag identification module and a database. The tag identification module scans the identification tag to identify the first control instruction. The database is electrically connected to the tag identification module to store the first control instruction.

Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.

Abstract: A semiconductor device includes a magnetic random access memory (MRAM). The MRAM comprises a plurality of MRAM cells including a first type MRAM cell and a second type MRAM cell. Each of the plurality of MRAM cells includes a magnetic tunneling junction (MTJ) layer including a pinned magnetic layer, a tunneling barrier layer and a free magnetic layer. A size of the MTJ film stack of the first type MRAM cell is different from a size of the MTJ film stack of the second type MRAM cell. In one or more of the foregoing and following embodiments, a width of the MTJ film stack of the first type MRAM cell is different from a width of the MTJ film stack of the second type MRAM cell.

Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first transistor configured to generate a voltage difference based on a first current and an activation voltage, and is configured to output the activation voltage and a bias voltage based on the voltage difference. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to receive the activation voltage and conduct a second current responsive to the drive voltage and the activation voltage.

Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

Abstract: A ratchet wrench is provided, including: a main body and a handling assembly. The main body includes a head portion being assembled with a ratchet head and a handling portion remote from the head portion. The handling assembly includes a casing coveringly disposed on the handling portion, and the casing defines a receiving space which is configured to receive at least one object and has at least one opening disposed therethrough. Part of an outer surface of the handling portion is flush with or protrusive beyond the at least one opening, and a material of the handling portion is different from a material of the casing.

Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.

Abstract: A wide input voltage range power converter circuit in a one-stage-two-switch configuration has a power input terminal, a switch node connected to the power input terminal, a transformer, two electronic switches, a pulse width modulation (PWM) circuit, and an output circuit. An input side of the transformer has a first winding and a second winding that are connected to the switch node. An output side of the transformer has an output winding. A turns ratio between the first winding and the output winding is different from a turns ratio between the second winding and the output winding. The two electronic switches are respectively connected to the first winding and the second winding in series. The PWM circuit is connected to the power input terminal and control terminals of the two electronic switches. The output circuit is connected to the output winding.