Patents by Inventor Cheng Chou

Cheng Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230236929
    Abstract: A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.
    Type: Application
    Filed: March 14, 2023
    Publication date: July 27, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zheng-Jun LIN, Pei-Ling TSENG, Hsueh-Chih YANG, Chung-Cheng CHOU, Yu-Der CHIH
  • Publication number: 20230223091
    Abstract: A memory sector with trimmed reference currents, including eight unit cells corresponding to an even word line and eight unit cells corresponding to an odd word line, and each unit cell has erased state and programmed state, wherein the logic state of unit cell corresponding to the odd word line is determined by a first reference current based on cell currents of the 8 unit cells corresponding to the even word line in programmed state and cell currents of the eight unit cells corresponding to the odd word line in erased state, and the logic state of unit cell corresponding to the even word line is determined by a second reference current based on cell currents of the eight unit cells corresponding to the even word line in erased state and cell currents of the 8 unit cells corresponding to the odd word line in programmed state.
    Type: Application
    Filed: February 17, 2022
    Publication date: July 13, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Shan Ho, Ying-Ting Lin, Chung-Yi Luo, Kuo-Cheng Chou, Cheng-Hsiao Lai, Ming-Jen Chang, Yung-Tsai Hsu, Cheng-Chieh Cheng
  • Publication number: 20230203474
    Abstract: A compound, a solid carrier including the same and a method for preparing a nucleic acid are provided. The compound has a structure represented by Formula (1) as follows. In Formula (1), the definition of Y1, Y2, Z and * are the same as defined in the detailed description.
    Type: Application
    Filed: December 26, 2022
    Publication date: June 29, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Ming-Chun Lin, Hui-Ling Cheng, Chun-Ting Lai, Hua-Cheng Chou, Wei-Chin Huang, Chih-Hung Chen, Shu-Feng Chen
  • Publication number: 20230207005
    Abstract: A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.
    Type: Application
    Filed: May 31, 2022
    Publication date: June 29, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih
  • Publication number: 20230197617
    Abstract: A connecting structure includes a substrate, a first conductive feature, a second conductive feature, a third conductive feature over the first conductive feature, and a fourth conductive feature over the second conductive feature. The substrate includes a first region and a second region. The first conductive feature is disposed in the first region and has a first width. The second conductive feature is disposed in the second region and has a second width greater than the first width of the first conductive feature. The third conductive feature includes a first anchor portion surrounded by the first conductive feature. The fourth conductive feature includes a second anchor portion surrounded by the second conductive feature. A depth difference ratio between a depth of the first anchor portion and a depth of the second anchor portion is less than approximately 10%.
    Type: Application
    Filed: February 15, 2023
    Publication date: June 22, 2023
    Inventors: U-TING CHIU, YU-SHIH WANG, CHUN-CHENG CHOU, YU-FANG HUANG, CHUN-NENG LIN, MING-HSI YEH
  • Patent number: 11672181
    Abstract: A semiconductor device includes a magnetic random access memory (MRAM). The MRAM comprises a plurality of MRAM cells including a first type MRAM cell and a second type MRAM cell. Each of the plurality of MRAM cells includes a magnetic tunneling junction (MTJ) layer including a pinned magnetic layer, a tunneling barrier layer and a free magnetic layer. A size of the MTJ film stack of the first type MRAM cell is different from a size of the MTJ film stack of the second type MRAM cell. In one or more of the foregoing and following embodiments, a width of the MTJ film stack of the first type MRAM cell is different from a width of the MTJ film stack of the second type MRAM cell.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huang-Wen Tseng, Cheng-Chou Wu, Che-Jui Chang
  • Publication number: 20230148861
    Abstract: An optical system and an operating method thereof are disclosed. The optical system includes a light source device, a gaze module and a fundus detection device. The light source device includes a light source module, a light intensity modulation module and a lens module. The light source module is used to emit a therapy light to an eye. The light intensity modulation module is used to modulate an intensity of the therapy light. The lens module is used to control a depth of the therapy light. The gaze module is used to be gazed by the eye to fix a fundus of the eye. The fundus detection device and the light source device are integrated to detect the fundus to obtain a fundus image.
    Type: Application
    Filed: November 10, 2022
    Publication date: May 18, 2023
    Inventors: William WANG, Hsuan-Hao CHAO, Sung-Yang WEI, Chung-Cheng CHOU
  • Publication number: 20230154799
    Abstract: A method includes forming patterned masks over a semiconductor substrate; etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins; performing an annealing process using a hydrogen containing gas to smooth surfaces of the semiconductor fins; after performing the annealing process, selectively forming a first liner on the smoothed surfaces of the semiconductor fins, while leaving surfaces of the patterned masks exposed by the first liner; filling the trench with a dielectric material; and etching back the first liner and the dielectric material to form an isolation structure between the semiconductor fins.
    Type: Application
    Filed: January 6, 2023
    Publication date: May 18, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Cheng CHOU, Shiu-Ko JANGJIAN, Cheng-Ta WU
  • Publication number: 20230154765
    Abstract: A method includes bonding a first wafer to a second wafer, and performing a trimming process on the first wafer. An edge portion of the first wafer is removed. After the trimming process, the first wafer has a first sidewall laterally recessed from a second sidewall of the second wafer. A protection layer is deposited and contacting a sidewall of the first wafer, which deposition process includes depositing a non-oxygen-containing material in contact with the first sidewall. The method further includes removing a horizontal portion of the protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.
    Type: Application
    Filed: February 16, 2022
    Publication date: May 18, 2023
    Inventors: Chia Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
  • Publication number: 20230134020
    Abstract: An optical device including a positioning module, a multi-band light-source module, a tracking and locking module, a monitoring module and a control module is disclosed. The positioning module positions eyes according to their characteristics. The multi-band light source module is coupled to the positioning module. After the positioning module positions eyes, the multi-band light-source module emits multi-band light to eyes. The tracking and locking module tracks and locks eyes and provides first information including whether eyes are locked. The monitoring module monitors eyes and provides second information including whether eyes are emitted by the multi-band light for a default time. The control module is coupled to the tracking and locking module, the monitoring module and the multi-band light-source module to generate a control signal according to the first information and the second information to control the multi-band light-source module to continuously or stop emitting the multi-band light to eyes.
    Type: Application
    Filed: October 17, 2022
    Publication date: May 4, 2023
    Inventors: Yun-Hsuan LIN, William WANG, Chung-Cheng CHOU
  • Patent number: 11636896
    Abstract: A memory circuit includes a first driver circuit, a first column of memory cells coupled to the first driver circuit, a first current source, a tracking circuit configured to track a leakage current of the first column of memory cells, and a footer circuit coupled to the first column of memory cells, the first current source and the tracking circuit.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: April 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-I Su, Chung-Cheng Chou, Yu-Der Chih, Zheng-Jun Lin
  • Publication number: 20230113903
    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 13, 2023
    Inventors: Yu-Der CHIH, Chung-Cheng Chou, Wen-Ting Chu
  • Publication number: 20230107649
    Abstract: An automatic eye test device and an automatic eye test method are disclosed. The automatic eye test device includes an automatic positioning module, an automatic test module and an automatic analysis module. The automatic positioning module is configured to automatically complete positioning of an eye of a person to be tested. The automatic test module is coupled to the positioning module and configured to automatically test the eye of the person to be tested to obtain a test result. The automatic analysis module is coupled to the automatic test module and configured to automatically analyze the test result to provide a personalized test suggestion for the person to be tested.
    Type: Application
    Filed: July 27, 2022
    Publication date: April 6, 2023
    Inventors: William WANG, Chung-Ping CHUANG, Chun Nan LIN, Chung-Cheng CHOU
  • Patent number: 11609185
    Abstract: A portable ring-type fluorescence optical system for observing microfluidic channel and an operating method thereof are disclosed. The portable ring-type fluorescence optical system includes a photographic chip, a first polarizer, an objective lens, a ring-type fluorescent light source, a biological sample on a microfluidic chip, a second polarizer and a bottom illumination light source arranged in order from top to bottom. The ring-type fluorescent light source is used to generate a ring-type fluorescent light to the biological sample on the microfluidic chip. The objective lens is used to magnify a fluorescent image of the biological sample on the microfluidic chip to focus on the photographic chip. The first polarizer disposed under the photographic chip and the second polarizer disposed under the biological sample form a non-zero angle to each other to block reflected lights that the biological sample reflects the lights emitted by the bottom illumination light source.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 21, 2023
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Sung-Yang Wei, Long Hsu, Hwan-You Chang, Huang-Ming Chen, Jen-Tsan Chi, Chung-Cheng Chou, Yuh-Cherng Lai, Hung-Yu Yeh, Ting-Chou Wei, Yun-Ting Yao, Cheng-Hsien Liu
  • Patent number: 11609815
    Abstract: A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zheng-Jun Lin, Pei-Ling Tseng, Hsueh-Chih Yang, Chung-Cheng Chou, Yu-Der Chih
  • Publication number: 20230072287
    Abstract: A resistive random-access memory (RRAM) circuit includes an RRAM device configured to output a cell current responsive to a bit line voltage, and a current limiter including an input terminal coupled to the RRAM device, first and second parallel current paths configured to conduct the cell current between the input terminal and a reference voltage node, and an amplifier configured to generate a first signal responsive to a voltage level at the input terminal and a reference voltage level. Each of the first and second current paths includes a switching device configured to selectively conduct a portion of the cell current responsive to the first signal.
    Type: Application
    Filed: November 10, 2022
    Publication date: March 9, 2023
    Inventors: Chung-Cheng CHOU, Zheng-Jun LIN, Pei-Ling TSENG
  • Publication number: 20230068714
    Abstract: A method for manufacturing a semiconductor device includes forming one or more work function layers over a semiconductor structure. The method includes forming a hardmask layer over the one or more work function layers. The method includes forming an adhesion layer over the hardmask layer. The method includes removing a first portion of a patternable layer that is disposed over the hardmask layer. The adhesion layer comprises an organic acid that concurrently bonds metal atoms of the hardmask layer and phenol groups of the patternable layer, thereby preventing an etchant from penetrating into a second portion of the patternable layer that still remains over the hardmask layer.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Chou, Ying-Liang Chuang, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20230063758
    Abstract: A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zheng-Jun LIN, Pei-Ling TSENG, Hsueh-Chih YANG, Chung-Cheng CHOU, Yu-Der CHIH
  • Publication number: 20230065104
    Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.
    Type: Application
    Filed: November 7, 2022
    Publication date: March 2, 2023
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Pei-Ling Tseng
  • Publication number: 20230067300
    Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Chou, Yu-Fang Huang, Kuo-Ju Chen, Ying-Liang Chuang, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang