Patents by Inventor Cheng Chou

Cheng Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210139592
    Abstract: An anti-PD-L1 antibody, or an antigen-binding fragment thereof, comprising: a heavy chain variable region comprising the three CDRs with the sequences of SEQ ID NOs: 2-4, 6-8, 10-12, 14-16, or 18-20; and/or a light chain variable region comprising the three CDRs with the sequences of SEQ ID NOs: 22-24, 26-28, 30-32, 34-36, or 38-40, wherein the antibody is a chimeric, humanized, composite, or human antibody.
    Type: Application
    Filed: July 14, 2019
    Publication date: May 13, 2021
    Applicant: Development Center for Biotechnology
    Inventors: Cheng-Chou YU, Shih-Rang YANG, Tsung-Han HSIEH, Mei-Chi CHAN, Shu-Ping YEH, Chuan-Lung HSU, Ling-Yueh HU, Chih-Lun HSIAO
  • Patent number: 10991426
    Abstract: A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Cheng Chou, Tien-Yen Wang
  • Publication number: 20210118499
    Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Inventors: Chien-An Lai, Chung-Cheng Chou, Yu-Der Chih
  • Publication number: 20210119531
    Abstract: A system includes a charge pump system having a plurality of enable signal input terminals and an output terminal, the charge pump system configured to provide an output voltage at the output terminal; and a detection circuit connected to the enable terminals and the output terminal of the charge pump system, the detection circuit configured to compare the charge pump system output voltage to a plurality of predefined input detection voltage levels, and to selectively output a plurality of enable signals to the charge pump system enable signal input terminals in response to the comparison.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Inventors: Chung-Cheng Chou, Tien-Yen Wang
  • Patent number: 10982305
    Abstract: The present teaching is generally directed to soft magnetic alloys. In particular, the present teaching is directed to soft magnetic alloys including Samarium (“Sm”). In a non-limiting embodiment, an Sm-containing magnetic alloy is described including 15 wt % to 55 wt % of Cobalt (“Co”), less than 2.5 wt % of Sm, and 35 wt % to 75 wt % of Iron (“Fe”). The Sm-containing magnetic alloy may further include at least one element X, selected from a group including Vanadium (“V”), Boron (“B”), Carbon (“C”), Chromium (“Cr”), Manganese (“Mn”), Molybdenum (“Mo”), Niobium (“Nb”), Nickel (“Ni”), Titanium (“Ti”), Tungsten (“W”), and Silicon (“Si”). The Sm-containing magnetic alloy may further have a magnetic flux density of at least 2.5 Tesla.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 20, 2021
    Assignees: TAIWAN POWDER TECHNOLOGIES CO., LTD., CHINA POWDER TECHNOLOGIES CO., LTD., HPM LABS CO., LTD.
    Inventors: Kuen-Shyang Hwang, Guo-Jiun Shu, Fang-Cheng Chou
  • Patent number: 10975889
    Abstract: A fan module and an electronic device are provided. The fan module includes a hub and a plurality of blades. The blades are mounted around the hub, and each of the blades has a first end that is connected to a periphery of the hub and a second end that is relatively away from the hub. A first axial direction distance in the axial direction is provided between a first point of the first end that is relatively away from the top surface and the top surface. A second axial direction distance in the axial direction is provided between a second point of the first end that is near the top surface and the top surface. A ratio of the second axial direction distance to the first axial direction distance is 0.4 to 0.5.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: April 13, 2021
    Assignee: Coretronic Corporation
    Inventors: Shih-Hang Lin, Chih-Cheng Chou
  • Patent number: 10971544
    Abstract: Methods for forming a magneto-resistive memory device and a capacitor in an interconnect structure are disclosed herein. An exemplary method includes forming a first level interconnect metal layer and a second level interconnect metal layer of an interconnect structure. The method further includes simultaneously forming a first plurality of layers in a first region of the interconnect structure and a second plurality of layers in a second region of the interconnect structure, wherein the first plurality of layers and the second plurality of layers are disposed between the first level interconnect metal layer and the second level interconnect metal layer. The first plurality of layers is configured as a magneto-resistive memory device. The second plurality of layers is configured as the capacitor. The magneto-resistive memory device and the capacitor are each coupled to the first level interconnect metal layer and the second level interconnect metal layer.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chung-Cheng Chou, Ya-Chen Kao, Tien-Wei Chiang
  • Publication number: 20210096586
    Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.
    Type: Application
    Filed: September 2, 2020
    Publication date: April 1, 2021
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Chin-I Su
  • Patent number: 10950303
    Abstract: A circuit includes a bias voltage generator and a current limiter. The bias voltage generator is configured to receive a first reference voltage and output a bias voltage responsive to a first current and the first reference voltage. The current limiter is configured to receive a second current at an input terminal, a second reference voltage, and the bias voltage, and, responsive to the second reference voltage and a voltage level of the input terminal, limit the second current to a current limit level, the voltage level of the input terminal being based on the bias voltage.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Cheng Chou, Pei-Ling Tseng, Zheng-Jun Lin
  • Publication number: 20210074581
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 11, 2021
    Inventors: Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo, Po-Cheng Shih, Tze-Liang Lee, Jun-Yi Ruan
  • Patent number: 10936175
    Abstract: A computing device obtains multimedia content relating to a user of the computing device and generates a user interface. In a first mode of operation, the user interface displays a plurality of graphical thumbnails each depicting a cosmetic result, each graphical thumbnail corresponding to a cosmetic template, each of the plurality of cosmetic templates comprising a listing of cosmetic effects utilized for achieving each corresponding cosmetic result. A selection is obtained from the user of one or more graphical thumbnails to select one or more cosmetic templates. Responsive to operating in the second mode of operation, a corresponding listing of cosmetic effects is displayed for each of the one or more selected cosmetic templates and obtaining selection of one or more of the displayed cosmetic effects.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: March 2, 2021
    Assignee: PERFECT CORP.
    Inventors: Cheng Chou, Tsung-Peng Yen, Chieh-Chung Wu
  • Publication number: 20210054268
    Abstract: A yellow light emitting device may have a light source and a color converter wherein at most 1% of the total emitted radiant power of the yellow light emitting device is emitted in a wavelength range shorter than 520 nm, as well as the use of the yellow light emitting device.
    Type: Application
    Filed: March 19, 2019
    Publication date: February 25, 2021
    Applicants: BASF SE, BASF Taiwan Ltd.
    Inventors: Hannah Stephanie MANGOLD, Sorin IVANOVICI, Martin KOENEMANN, Siang Fu HONG, Chia Wei TSAI, Yen Te LEE, Wei Cheng CHOU
  • Patent number: 10930344
    Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first current path configured to receive a first current from a current source, and output a bias voltage based on a voltage difference generated from conduction of the first current in the first current path. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to conduct a second current responsive to the drive voltage.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Cheng Chou, Hsu-Shun Chen, Chien-An Lai, Pei-Ling Tseng, Zheng-Jun Lin
  • Patent number: 10922737
    Abstract: A interactive product recommendation method is provided, including: selecting a target product from the plurality of products; loading the product information of the target product; generating a product list according to the product characteristics corresponding to the target product and the user preferences corresponding to at least one user; generating a first label list based on at least one product characteristics corresponding to the target product and the user preferences corresponding to the user, where the first label list has a plurality of first labels corresponding to different product features; and displaying the product information, the product list and the first label list in a user interface. When clicking the icon, displaying another user interface corresponding to the clicked icon. When clicking the first label, updating the product list according to the clicked first label.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: February 16, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien-Yang Guo, Yun-Cheng Chou, Chin-Sheng Yeh, Chih-Pin Su, Shin-Yi Wu
  • Publication number: 20210043518
    Abstract: A method for manufacturing a semiconductor structure includes etching trenches in a semiconductor substrate to form a semiconductor fin between the trenches; converting sidewalls of the semiconductor fin into hydrogen-terminated surfaces each having silicon-to-hydrogen (S—H) bonds; after converting the sidewalls of the semiconductor fin into the hydrogen-terminated surfaces, depositing a dielectric material overfilling the trenches; and etching back the dielectric material to fall below a top surface of the semiconductor fin.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Cheng CHOU, Shiu-Ko JANGJIAN, Cheng-Ta WU
  • Patent number: 10916305
    Abstract: A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state; a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state; and an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: February 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lien Linus Lu, Yu-Der Chih, Chung-Cheng Chou, Tong-Chern Ong
  • Publication number: 20210031341
    Abstract: This invention provides an electric screwdriver with an integrated torque adjustment and sensing function, comprising a torque sensor connected between an electric motor and a torque adjuster. The torque sensor comprises a transmission shaft connected to the motor shaft by the shaft, a torque sensing component and at least one planetary gear set. The planetary gear set has a torque output component. The transmission shaft transmits the speed reduced rotational force through the torque output component to drive the output shaft to output a target torque which can be adjusted by the adjuster. The torque sensing component senses the operating torque between the transmission shaft and the torque output component of the torque sensor, thereby assembling to improve the problem that the conventional electric screwdriver can only adjust but cannot accurately sense the operating torque.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 4, 2021
    Inventors: YUN-LUN CHANG, CHIH-CHENG CHOU, YUEH-YANG HU
  • Patent number: 10910216
    Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: February 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia Cheng Chou, Li Chun Te, Po-Cheng Shih, Tien-I Bao
  • Publication number: 20210013399
    Abstract: A semiconductor device includes a magnetic random access memory (MRAM). The MRAM comprises a plurality of MRAM cells including a first type MRAM cell and a second type MRAM cell. Each of the plurality of MRAM cells includes a magnetic tunneling junction (MTJ) layer including a pinned magnetic layer, a tunneling barrier layer and a free magnetic layer. A size of the MTJ film stack of the first type MRAM cell is different from a size of the MTJ film stack of the second type MRAM cell. In one or more of the foregoing and following embodiments, a width of the MTJ film stack of the first type MRAM cell is different from a width of the MTJ film stack of the second type MRAM cell.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 14, 2021
    Inventors: Huang-Wen TSENG, Cheng-Chou WU, Che-Jui CHANG
  • Publication number: 20210003446
    Abstract: A spectrometer is disclosed. The spectrometer includes a fiber input, a collimator lens, a rotating shaft, a grating, a focal lens and a focal plane which have arranged in order. A broadband incident light of the fiber input becomes a first parallel beam through the collimator lens and separated by the grating into multiple parallel beams of different wavelengths and then focused by the focal lens to emit an output beams to an imaging position on the focal plane. The spectrometer can rotate the collimator lens and fiber input to change the imaging position on the focal plane.
    Type: Application
    Filed: June 3, 2020
    Publication date: January 7, 2021
    Inventors: William WANG, Che-Liang TSAI, Chung-Cheng CHOU