Abstract: An apparatus for parity data management receives a write command and write data from a computing device. The apparatus also builds a parity control structure corresponding to updating a redundant disk array with the write data and stores the parity control structure in a persistent memory buffer of the computing device. The apparatus also updates the redundant disk array with the write data in accordance with a parity control map and restores the RAID controller parity map from the parity control structure as part of a data recovery operation if updating the redundant disk array with the write data is interrupted by a RAID controller failure resulting in a loss of the RAID controller parity map. In certain embodiments, the parity control structure is a RAID controller parity map.

Abstract: Provided are a method, system, and program for handling a fabric failure. A module intercepts a signal indicating a failure of a path in a fabric providing a connection to a shared device. The module generates an interrupt to a device driver in an operating system providing an interface to the shared device that is inaccessible due to the path failure. The device driver requests information from the module on a status of a plurality of devices that are not accessible due to the path failure and receives information indicating the inaccessible device. The device driver reconfigures to discontinue use of the inaccessible device.

Abstract: Provided are a method, system, and program for configuring shared devices over a fabric. A module in a first processing complex configures a first part of a fabric enabling communication with a set of devices accessible through the first part of the fabric. The module detects a located device accessible through a second part of the fabric, wherein a second processing complex is designated to configure the second part of the fabric and the located device. The module determines whether the second processing complex is available in response to detecting the uninitialized device. The module passes to a device driver in the first processing complex an uninitialized property for the located device. The device driver requests the module to configure the second part of the fabric to enable access to the located device over the second part of the fabric in response to determining that the located device has the uninitialized property.

Abstract: Provided are a method, system, and article of manufacture, wherein in certain embodiments, a plurality of logical memory blocks corresponding to a memory in a computational device are allocated. An attribute is associated with at least one logical memory block, wherein the attribute indicates whether the at least one logical memory block can be swapped from the memory, and wherein physical blocks corresponding to the at least one logical memory block are contiguous.

Abstract: In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.

Abstract: A method of verifying the passage of a data write across a bus is provided including sending the data write from an originator across the bus to a target, counting the number of data entries received at the target with a counter, and transmitting a return echo write from the target across the bus to a return address. The method further includes attaching the counter value to other data associated with the return echo write and polling the return address. The method allows determination of the completion of a data write by comparing the number of data entries included in the data write with the counter value polled from the return address. Alternatively, in a data streaming environment the progress of a data write may be determined by comparing the number of data entries included in the data write at a select point in time with the counter value polled from the return address. Typical data entries which are counted may include, but are not limited to, bytes, words, double words, or similar data quantities.

Abstract: A determination is made as to whether a configuration indicator associated with a resource indicates a delayed configuration of the resource, wherein the resource is shared by a plurality of processing complexes via a bus, and wherein if the delayed configuration of the resource is indicated then the resource is prevented from being configured during initial program loads of the plurality of processing complexes. The resource is configured by only one of the of plurality of processing complexes that shares the resource, in response to determining that the configuration indicator associated with the resource indicates the delayed configuration of the resource.

Abstract: Provided are a method, system, and article of manufacture, wherein a command is received at a first computational device coupled to a first adapter that is capable of allowing access to a data storage to the first computational device. The first computational device sends the command to a second computational device. The command is processed by a second adapter coupled to the second computational device, wherein the second adapter allows the second computational device to access the data storage, and wherein the second adapter accesses memory in the first computational device to process the command. In certain embodiments, the first adapter that allows the first computational device to access the data storage has failed.

Abstract: An apparatus for parity data management receives a write command and write data from a computing device. The apparatus also builds a parity control structure corresponding to updating a redundant disk array with the write data and stores the parity control structure in a persistent memory buffer of the computing device. The apparatus also updates the redundant disk array with the write data in accordance with a parity control map and restores the RAID controller parity map from the parity control structure as part of a data recovery operation if updating the redundant disk array with the write data is interrupted by a RAID controller failure resulting in a loss of the RAID controller parity map. In certain embodiments, the parity control structure is a RAID controller parity map.

Abstract: Provided are a method, system, deployment and article of manufacture, for variable length file entry navigation. In one embodiment, a first file entry size portion of a first entry marker at a first end of a file entry is read. A position of a second entry marker at a second end of the file entry may be calculated as a function of the first file entry size portion. A determination may be made as to whether file data at the calculated position is a second entry marker, and if so whether the file data between said first and second entry markers is a valid entry by comparing the first entry size portion of the first entry marker to a second file entry size portion of the second entry marker. Other embodiments are described and claimed.

Abstract: Provided are a method, system, and program for handling a fabric failure. A module intercepts a signal indicating a failure of a path in a fabric providing a connection to a shared device. The module generates an interrupt to a device driver in an operating system providing an interface to the shared device that is inaccessible due to the path failure. The device driver requests information from the module on a status of a plurality of devices that are not accessible due to the path failure and receives information indicating the inaccessible device. The device driver reconfigures to discontinue use of the inaccessible device.

Abstract: A method, system and program product save state data in a multi-processor system. A problem in the multi-processor system is detected and a statesave thread is spawned for each processor in the system. Each statesave thread directs a processor, in parallel with the other processors to attempt to identify a component in the system having a status of “incomplete”, indicating that state data of the component remains to be offloaded. When a component having a status of “incomplete” is identified, the processor executes statesave code to offload state data from the identified component. Upon completion of the state data offload from the identified component, the processor changes the status of the component to “complete”. The foregoing processes are repeated until no components are identified in the system having a status of “incomplete”.

Abstract: Provided is a method for handling a fabric failure. A module intercepts a signal indicating a failure of a path in a fabric providing a connection to a shared device. The module generates an interrupt to a device driver in an operating system providing an interface to the shared device that is inaccessible due to the path failure. The device driver requests information from the module on a status of a plurality of devices that are not accessible due to the path failure and receives information indicating the inaccessible device. The device driver reconfigures to discontinue use of the inaccessible device.

Abstract: DMA mapping for adapters configured to communicated with respect to a computer processor memory structure via DMA and configured to have DMA mapping space for control information and data. The adapters are separated into groups. The control information DMA mapping of the adapters is separated into at least three types: type “H” mapping, type “D” mapping, and shared mapping. The type “H” mapping and the shared mapping are applied to one group of adapters for the DMA mapping space for control information, such as host adapters, and the type “D” mapping and the shared mapping are applied to another group, such as device adapters, and the type “H” mapping of the one group and the type “D” mapping of another group are overlayed in the DMA mapping space for control information for the respective adapters.

Abstract: DMA mapping for adapters configured to communicate with respect to a computer processor memory structure via DMA and configured to have DMA mapping space for control information and data. The adapters are separated into groups. The control information DMA mapping of the adapters is separated into at least three types: type “H” mapping, type “D” mapping, and shared mapping. The type “H” mapping and the shared mapping are applied to one group of adapters for the DMA mapping space for control information, such as host adapters, and the type “D” mapping and the shared mapping are applied to another group, such as device adapters, and the type “H” mapping of the one group and the type “D” mapping of the another group are overlayed in the DMA mapping space for control information for the respective adapters.

Abstract: An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

Abstract: An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

Abstract: In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.

Abstract: In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.

Abstract: Provided are a method, system, and article of manufacture, wherein in certain embodiments, a plurality of logical memory blocks corresponding to a memory in a computational device are allocated. An attribute is associated with at least one logical memory block, wherein the attribute indicates whether the at least one logical memory block can be swapped from the memory, and wherein physical blocks corresponding to the at least one logical memory block are contiguous.