Abstract: Provided are a method, system, and article of manufacture, wherein in certain embodiments, a plurality of logical memory blocks corresponding to a memory in a computational device are allocated. An attribute is associated with at least one logical memory block, wherein the attribute indicates whether the at least one logical memory block can be swapped from the memory, and wherein physical blocks corresponding to the at least one logical memory block are contiguous.

Abstract: An apparatus, system, and method are disclosed for concurrently relocating a RAID array. The apparatus includes an identification module, a designation module, and an implementation module. The identification module identifies an availability of a physical device within a donor arrayed storage device to offload a source drive of a relocation enclosure. The designation module designates an available physical device as a target drive and thereby designate the target drive and the source drive as a linked pair;. The implementation module implements a mirroring relationship between the target drive and the source drive. The apparatus, system, and method provide a dynamic relocation of the raid array, minimizing system downtime and maximizing efficient utilization of system resources.

Abstract: A method, system and program product save state data in a multi-processor system. A problem in the multi-processor system is detected and a statesave thread is spawned for each processor in the system. Each statesave thread directs a processor, in parallel with the other processors to attempt to identify a component in the system having a status of “incomplete”, indicating that state data of the component remains to be offloaded. When a component having a status of “incomplete” is identified, the processor executes statesave code to offload state data from the identified component. Upon completion of the state data offload from the identified component, the processor changes the status of the component to “complete”. The foregoing processes are repeated until no components are identified in the system having a status of “incomplete”.

Abstract: In a data processing system having multiple input/output adapters, a DMA memory block is assigned to each adapter. The DMA memory block has a data area and a generic common control area. All adapters have the same translation control entry for the control area. The control area includes a mapped page assigned to each adapter request and an unmapped buffer space interposed between the mapped pages. By mapping the generic DMA memory, memory space which is not required by an adapter is not mapped unnecessarily. Because the generic DMA memory space is part of each adapter's DMA memory space, adapters are unable to write to partitions to which they do not belong and the possibility of cross-partition memory writes is reduced. Moreover, runaway writes to dedicated DMA memory space may be caught as soon as they occur.

Abstract: A method, apparatus and program storage device for providing light weight system calls to improve user mode performance is disclosed. A range of system call code for the light weight system calls is provided in a system call table. The light weight system calls skip the code for saving and restore processor context.

Abstract: A method, apparatus and program storage device for providing a no context switch attribute that allows a user mode thread to become a near interrupt disabled priority is disclosed. A thread includes a no context switch attribute. Control of a thread based on the no context switch attribute is much more efficient than the real-time priority because the no context switch attribute bypasses the overhead of scheduling. Moreover, the no context switch attribute may be used to detect whether a thread performs any undesirable operations that can cause the thread to become suspended while in a critical section. The no context switch attribute is configurable to indicate whether execution of the thread can be suspended.

Abstract: A method, apparatus and program storage device for providing an anchor pointer in an operating system context structure for improving the efficiency of accessing thread specific data is provided. A kernel thread context structure is maintained in memory. A thread accesses a pointer memory in the kernel specific context structure and sets a value within the pointer memory that addresses data specific to the thread.

Abstract: A method, apparatus and program storage device that provides a user mode device interface for enabling software reuse. The user mode device interface allows device interface requests to be sent and received, including commands and data structures, via socket communication. A device state machine on the client side is implemented in a set of shared functions that can be incorporated by all applications that want to communicate to a particular service provider. The service provider offers the software functions over a user mode device interface via socket communication. The device state machine on the service provider side is embedded in the socket server implementation. The interaction between the state machines on both client and server sides ensures a device interface request is properly handled.

Abstract: Provided are a method, system, and program for handling a fabric failure. A module intercepts a signal indicating a failure of a path in a fabric providing a connection to a shared device. The module generates an interrupt to a device driver in an operating system providing an interface to the shared device that is inaccessible due to the path failure. The device driver requests information from the module on a status of a plurality of devices that are not accessible due to the path failure and receives information indicating the inaccessible device. The device driver reconfigures to discontinue use of the inaccessible device.

Abstract: In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.

Abstract: Provided are a method, system and article of manufacture, wherein a first application executes at least two threads corresponding to a simultaneous multi-threaded processor whose resources have been acquired by the first application. The at least two threads are synchronized before releasing the simultaneous multi-threaded processor to a second application.

Abstract: A method of verifying the passage of a data write across a bus is provided including sending the data write from an originator across the bus to a target, counting the number of data entries received at the target with a counter, and transmitting a return echo write from the target across the bus to a return address. The method further includes attaching the counter value to other data associated with the return echo write and polling the return address. The method allows determination of the completion of a data write by comparing the number of data entries included in the data write with the counter value polled from the return address. Alternatively, in a data streaming environment the progress of a data write may be determined by comparing the number of data entries included in the data write at a select point in time with the counter value polled from the return address. Typical data entries which are counted may include, but are not limited to, bytes, words, double words, or similar data quantities.

Abstract: Provided are a method, system, and article of manufacture, wherein a command is received at a first computational device coupled to a first adapter that is capable of allowing access to a data storage to the first computational device. The first computational device sends the command to a second computational device. The command is processed by a second adapter coupled to the second computational device, wherein the second adapter allows the second computational device to access the data storage, and wherein the second adapter accesses memory in the first computational device to process the command. In certain embodiments, the first adapter that allows the first computational device to access the data storage has failed.

Abstract: Provided are a method, system, and program for configuring shared devices over a fabric. A module in a first processing complex configures a first part of a fabric enabling communication with a set of devices accessible through the first part of the fabric. The module detects a located device accessible through a second part of the fabric, wherein a second processing complex is designated to configure the second part of the fabric and the located device. The module determines whether the second processing complex is available in response to detecting the uninitialized device. The module passes to a device driver in the first processing complex an uninitialized property for the located device. The device driver requests the module to configure the second part of the fabric to enable access to the located device over the second part of the fabric in response to determining that the located device has the uninitialized property.

Abstract: A technique for handling hardware errors in a computing system, such as a data storage facility, while avoiding a system crash. An interface is registered with an operating system of the computing system to process hardware errors. When a hardware error is detected, the interface checks an error register to identify the adapter that likely causes the error, and quarantines, e.g., blocks off, the offending adapter from the computing system. The interface then notifies the operating system that the error has been handled, thereby causing the operating system to bypass a system crash that would otherwise occur. The interface can be provided as a kernel extension of a device driver associated with the operating system.

Abstract: Provided are a method, system, deployment and article of manufacture, for variable length file entry navigation. In one embodiment, a first file entry size portion of a first entry marker at a first end of a file entry is read. A position of a second entry marker at a second end of the file entry may be calculated as a function of the first file entry size portion. A determination may be made as to whether file data at the calculated position is a second entry marker, and if so whether the file data between said first and second entry markers is a valid entry by comparing the first entry size portion of the first entry marker to a second file entry size portion of the second entry marker. Other embodiments are described and claimed.

Abstract: Provided are a method, system, and article of manufacture, wherein in certain embodiments a determination is made as to whether a configuration indicator associated with a resource indicates a delayed configuration of the resource, wherein the resource is shared by a plurality of processing complexes via a bus, and wherein if the delayed configuration of the resource is indicated then the resource is prevented from being configured during initial program loads of the plurality of processing complexes. The resource is configured by only one of the of plurality of processing complexes that shares the resource, in response to determining that the configuration indicator associated with the resource indicates the delayed configuration of the resource.

Abstract: Provided are a method, system, and article of manufacture, wherein in certain embodiments, a plurality of logical memory blocks corresponding to a memory in a computational device are allocated. An attribute is associated with at least one logical memory block, wherein the attribute indicates whether the at least one logical memory block can be swapped from the memory, and wherein physical blocks corresponding to the at least one logical memory block are contiguous.