Patents by Inventor Cheng Fu

Cheng Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12288382
    Abstract: A machine learning method for continual learning is provided, and the method includes following steps. Capturing an input image. Performing feature extraction on the input image by a plurality of sub-models to obtain a plurality of feature maps, where the sub-models correspond to a plurality of tasks, and the sub-models are determined by a neural network model and a plurality of channel-wise masks. Converting the feature maps into a plurality of energy scores. Selecting a target sub-model corresponding to a target task of the tasks from the sub-models according to the energy scores. Outputting a prediction result corresponding to the target task by the target sub-model.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: April 29, 2025
    Assignee: Wistron Corporation
    Inventors: Jiun-In Guo, Cheng-Fu Liou
  • Publication number: 20250046650
    Abstract: A method of wafer bonding includes the following operations. A first surface of the handle wafer, a second surface of the device wafer, or a combination thereof, is coated with water. When the first surface of the handle wafer is coated with water, the handle wafer is rotated at a first rotational speed. When the second surface of the device wafer is coated with water, the device wafer is rotated at a second rotational speed. When the first surface of the handle wafer and the second surface of the device wafer are coated with water, the handle wafer is rotated at a third rotational speed, and the device wafer is rotated at a fourth rotational speed. The first surface of the handle wafer and the second surface of the device wafer are bonded.
    Type: Application
    Filed: November 22, 2023
    Publication date: February 6, 2025
    Inventors: Wei-Jing CHENG, Cheng-Fu FAN
  • Publication number: 20240419972
    Abstract: An object detection method includes the following steps: detecting an environment signal, determining a task mode based on the environment signal, capturing an input image, performing feature extraction on the input image through a sub-model of a neural network model according to the task mode, where the sub-model of the neural network model includes a task-specific layer corresponding to the task mode, where a polarization mask of the task-specific layer determines the sub-model of the neural network model, and outputting an object detection result corresponding to the task mode.
    Type: Application
    Filed: August 14, 2023
    Publication date: December 19, 2024
    Applicant: Wistron Corporation
    Inventors: Jiun-In Guo, Cheng-Fu Liou
  • Patent number: 12159598
    Abstract: An e-paper display apparatus includes an e-paper display panel including multiple source lines, multiple gate selection lines, and multiple pixel circuits and a driver circuit coupled to the e-paper display panel and configured to output a driving signal to the gate selection line. The gate selection lines and the source lines are disposed along a first direction. The source lines corresponding to the gate selection line simultaneously receive respective data signals when the gate selection line is turned on. The driving signal includes a first period and a second period. The gate selection line is turned on during the first period, and the gate selection line is turned off during the second period. A time length of the first period is greater than a time length of the second period.
    Type: Grant
    Filed: October 31, 2023
    Date of Patent: December 3, 2024
    Assignee: E Ink Holdings Inc.
    Inventors: Jia-Hung Chen, An-Chi Liu, Yu-Mao Lin, Kuang Cheng Fu, Pei Ju Wu
  • Patent number: 12093405
    Abstract: A method and a system for automatically loading parameters, and a client-end server thereof are provided, and the method and the system, by a reversible information hiding technology, entrain various required parameters in an engineering drawing hiddenly to generate an encrypted file; and then, after decrypting the encrypted file by a pre-stored cipher key, obtain and automatically load the required parameters. Therefore, the parameters can be automatically loaded quickly, accurately and safely.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: September 17, 2024
    Assignee: Hiwin Technologies Corp.
    Inventors: Shang-Hua Tsai, Chi-Lun Cheng, Cheng-Fu Chou
  • Publication number: 20240233819
    Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 11, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
  • Publication number: 20240221692
    Abstract: An e-paper display apparatus includes an e-paper display panel including multiple source lines, multiple gate selection lines, and multiple pixel circuits and a driver circuit coupled to the e-paper display panel and configured to output a driving signal to the gate selection line. The gate selection lines and the source lines are disposed along a first direction. The source lines corresponding to the gate selection line simultaneously receive respective data signals when the gate selection line is turned on. The driving signal includes a first period and a second period. The gate selection line is turned on during the first period, and the gate selection line is turned off during the second period. A time length of the first period is greater than a time length of the second period.
    Type: Application
    Filed: October 31, 2023
    Publication date: July 4, 2024
    Applicant: E Ink Holdings Inc.
    Inventors: Jia-Hung Chen, An-Chi Liu, Yu-Mao Lin, Kuang Cheng Fu, Pei Ju Wu
  • Publication number: 20240135990
    Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 25, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
  • Patent number: 11951571
    Abstract: A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. In the laser step, a plastic package material covering on each of the cutting streets is removed via a laser beam. In the plating step, a plurality of plating surfaces are disposed on a plurality of areas of the leadframe without the plastic package material. In the singulation step, the cutting streets of the leadframe are cut to form the package structure.
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: April 9, 2024
    Assignee: INTEGRATED SILICON SOLUTION INC.
    Inventors: Cheng-Fu Yu, Kai-Jih Shih, Yi-Jung Liu
  • Publication number: 20240076586
    Abstract: The present disclosure provides a formula of a remover reagent for a cured silicone sealant and a method using the same. The remover reagent is prepared from an acid catalyst and a solvent each having a high boiling point and a high flash point. The acid catalyst is benzenesulfonic acid or alkylbenzenesulfonic acid. The solvent is mineral oil and/or silicone oil. The cured silicone sealant is first soaked with the remover reagent for 30 to 120 min, and then baked at a high temperature of 80 to 120° C. for 10 min or above into debris or powder, whereby the cured silicone sealant with a thickness of 10 mm or above can be removed. Moreover, the remover reagent has the advantages of readily available raw materials, high safety, environmentally friendliness, convenient preparation and good sealant removal effect, and thus, has good application prospects.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 7, 2024
    Inventors: Cheng FU, Shengyu GE, Huijun GUO, Liang ZHAO
  • Patent number: 11908516
    Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 20, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
  • Publication number: 20240047313
    Abstract: A package structure includes a leadframe, at least two dies, at least one spacer and a plastic package material. The leadframe includes a die pad. The dies are disposed on the die pad of the leadframe. The spacer is disposed between at least one of the dies and the die pad. The plastic package material is disposed on the leadframe, and covers the dies. A first minimum spacing distance is between one of a plurality of edges of the spacer and one of a plurality of edges of the die pad, a second minimum spacing distance is between one of a plurality of edges of the dies and one of the edges of the die pad, and the first minimum spacing distance is larger than the second minimum spacing distance.
    Type: Application
    Filed: November 3, 2022
    Publication date: February 8, 2024
    Inventors: Cheng-Fu YU, Kai-Jih SHIH, Chi-Yi WU
  • Patent number: D1013787
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: February 6, 2024
    Assignee: Aristocrat Technologies, Inc.
    Inventors: Rena Schoonmaker, Bruce Urban, Scott Hendrickson, Keith Chambers, Matthew McKay, Ariel David Turgel, Cheng-Fu Hsieh, Brian Bergeson
  • Patent number: D1042644
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: September 17, 2024
    Assignee: ARISTOCRAT TECHNOLOGIES AUSTRALIA PTY LIMITED
    Inventors: Bruce Urban, Rajendrasinh Jadeja, Cheng-Fu Hsieh
  • Patent number: D1044955
    Type: Grant
    Filed: November 1, 2023
    Date of Patent: October 1, 2024
    Assignee: Aristocrat Technologies, Inc.
    Inventors: Rena Schoonmaker, Bruce Urban, Scott Hendrickson, Keith Chambers, Matthew McKay, Ariel Turgel, Cheng-Fu Hsieh, Brian Bergeson
  • Patent number: D1046975
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: October 15, 2024
    Assignee: ARISTOCRAT TECHNOLOGIES AUSTRALIA PTY LIMITED
    Inventors: Bruce Urban, Rajendrasinh Jadeja, Cheng-Fu Hsieh
  • Patent number: D1046981
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: October 15, 2024
    Assignee: ARISTOCRAT TECHNOLOGIES AUSTRALIA PTY LIMITED
    Inventors: Michael Bristol, Rajendrasinh Jadeja, James Stair, Dominic DeMarco, Joseph Kaminkow, Ariel Turgel, Elliot Ortiz, Mark Hearn, Cheng-Fu Hsieh, Daniel Harden
  • Patent number: D1064083
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: February 25, 2025
    Assignee: Aristocrat Technologies Australia Pty Limited
    Inventors: Michael Berry, Timothy Francis Barbour, Bruce Edward Urban, Daniel Harden, Hirotomi Teranishi, Jase Ruggles, Cheng-Fu Hsieh, Ariel David Turgel
  • Patent number: D1071116
    Type: Grant
    Filed: May 24, 2023
    Date of Patent: April 15, 2025
    Assignee: AIRMATE ELECTRICAL (JIUJIANG) CO., LTD
    Inventors: Cheng-Fu Tsai, Jiaxin Zheng
  • Patent number: D1071117
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: April 15, 2025
    Assignee: AIRMATE ELECTRICAL (JIUJIANG) CO., LTD
    Inventors: Cheng-Fu Tsai, Jiaxin Zheng