Patents by Inventor Cheng Guo

Cheng Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8257501
    Abstract: In a plasma doping device according to the invention, a vacuum chamber (1) is evacuated with a turbo-molecular pump (3) as an exhaust device via a exhaust port 11 while a predetermined gas is being introduced from a gas supply device (2) in order to maintain the inside of the vacuum chamber (1) to a predetermined pressure with a pressure regulating valve (4). A high-frequency power of 13.56 MHz is supplied by a high-frequency power source (5) to a coil (8) provided in the vicinity of a dielectric window (7) opposed to a sample electrode (6) to generate inductive-coupling plasma in the vacuum chamber (1). A high-frequency power source (10) for supplying a high-frequency power to the sample electrode (6) is provided. Uniformity of processing is enhanced by driving a gate shutter (18) and covering a through gate (16).
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: September 4, 2012
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno, Hiroyuki Ito, Ichiro Nakayama, Cheng-Guo Jin
  • Patent number: 8252515
    Abstract: A method for removing a photoresist is disclosed. First, a substrate including a patterned photoresist is provided. Second, an ion implantation is carried out on the substrate. Then, a non-oxidative pre-treatment is carried out on the substrate. The non-oxidative pre-treatment provides hydrogen, a carrier gas and plasma. Later, a photoresist-stripping step is carried out so that the photoresist can be completely removed.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: August 28, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Cheng Chien, Chan-Lon Yang, Chiu-Hsien Yeh, Che-Hua Hsu, Zhi-Cheng Lee, Shao-Hua Hsu, Cheng-Guo Chen, Shin-Chi Chen, Zhi-Jian Wang
  • Patent number: 8232152
    Abstract: A removing method of a hard mask includes the following steps. A substrate is provided. At least two MOSFETs are formed on the substrate. An isolating structure is formed in the substrate and located between the at least two MOSFETs. Each of the MOSEFTs includes a gate insulating layer, a gate, a spacer and a hard mask on the gate. A protecting structure is formed on the isolating structure and the hard mask is exposed from the protecting structure. The exposed hard mask is removed to expose the gate.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: July 31, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Che-Hua Hsu, Shao-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen, Shin-Chi Chen, Hung-Ling Shih, Hung-Yi Wu, Heng-Ching Huang
  • Publication number: 20120186519
    Abstract: A plasma doping method and apparatus in which a prescribed gas is introduced into a vacuum container while being exhausted by a turbomolecular pump as an exhaust apparatus. The pressure in the vacuum container is kept at a prescribed value by a pressure regulating valve. High-frequency electric power of 13.56 MHz is supplied to a coil disposed close to a dielectric window which is opposed to a sample electrode, whereby induction-coupled plasma is generated in the vacuum container. Every time a prescribed number of samples have been processed, a dummy sample is subjected to plasma doping and then to heating. The conditions for processing of a sample are controlled so that the measurement value of the surface sheet resistance becomes equal to a prescribed value, whereby the controllability of the impurity concentration can be increased.
    Type: Application
    Filed: January 25, 2012
    Publication date: July 26, 2012
    Applicant: Panasonic Corporation
    Inventors: Tomohiro Okumura, Yuichiro Sasaki, Katsumi Okashita, Hiroyuki Ito, Bunji Mizuno, Cheng-Guo Jin, Ichiro Nakayama
  • Patent number: 8222128
    Abstract: A method for introducing impurities includes a step for forming an amorphous layer at a surface of a semiconductor substrate, and a step for forming a shallow impurity-introducing layer at the semiconductor substrate which has been made amorphous, and an apparatus used therefore. Particularly, the step for forming the amorphous layer is a step for irradiating plasma to the surface of the semiconductor substrate, and the step for forming the shallow impurity-introducing layer is a step for introducing impurities into the surface which has been made amorphous.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: July 17, 2012
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Bunji Mizuno, Cheng-Guo Jin
  • Publication number: 20120142157
    Abstract: The method of fabricating a semiconductor structure according to the present invention includes planarizing an inter-layer dielectric layer and further a hard mask to remove a portion of hard mask in a thickness direction. The remaining hard mask has a thickness less than the original thickness of the hard mask. The remaining hard mask and the dummy gate are removed to form a recess. After a gate material is filled into the recess, a gate with a relatively accurate height can be obtained.
    Type: Application
    Filed: December 7, 2010
    Publication date: June 7, 2012
    Inventors: Cheng-Guo Chen, Zhi-Cheng Lee, Shao-Hua Hsu, Jung-Tsung Tseng, Chien-Ting Lin, Cheng-Hsien Chou
  • Publication number: 20120139042
    Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having at least a dummy gate, a sacrificial layer covering sidewalls of the dummy gate and a dielectric layer exposing a top of the dummy gate formed thereon, forming a sacrificial layer covering sidewalls of the dummy gate on the substrate, forming a dielectric layer exposing a top of the dummy gate on the substrate, performing a first etching process to remove a portion of the sacrificial layer surrounding the top of the dummy gate to form at least a first recess, and performing a second etching process to remove the dummy gate to form a second recess. The first recess and the second recess construct a T-shaped gate trench.
    Type: Application
    Filed: December 7, 2010
    Publication date: June 7, 2012
    Inventors: Ssu-I Fu, I-Ming Tseng, En-Chiuan Liou, Cheng-Guo Chen
  • Patent number: 8183275
    Abstract: Certain novel substituted imidazoles are ligands of the human bombesin receptor and, in particular, are selective ligands of the human bombesin receptor subtype-3 (BRS-3). They are therefore useful for the treatment, control, or prevention of diseases and disorders responsive to the modulation of BRS-3, such as obesity, and diabetes.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: May 22, 2012
    Assignees: Merck Sharp & Dohme Corp., Albany Molecular Research, Inc.
    Inventors: Peter H. Dobbelaar, Christopher L. Franklin, Allan Goodman, Cheng Guo, Peter R. Guzzo, Mark Hadden, Shuwen He, Alan J. Henderson, Tianying Jian, Linus S. Lin, Jian Liu, Ravi P. Nargund, Megan Ruenz, Bruce J. Sargent, Iyassu K. Sebhat, Larry Yet
  • Publication number: 20120088368
    Abstract: A method of selectively removing a patterned hard mask is described. A substrate with a patterned target layer thereon is provided, wherein the patterned target layer includes a first target pattern and at least one second target pattern, and the patterned hard mask includes a first mask pattern on the first target pattern and a second mask pattern on the at least one second target pattern. A first photoresist layer is formed covering the first mask pattern. The sidewall of the at least one second target pattern is covered by a second photoresist layer. The second mask pattern is removed using the first photoresist layer and the second photoresist layer as a mask.
    Type: Application
    Filed: October 8, 2010
    Publication date: April 12, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Che-Hua Hsu, Shao-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen
  • Publication number: 20120070952
    Abstract: A removing method of a hard mask includes the following steps. A substrate is provided. At least two MOSFETs are formed on the substrate. An isolating structure is formed in the substrate and located between the at least two MOSFETs. Each of the MOSEFTs includes a gate insulating layer, a gate, a spacer and a hard mask on the gate. A protecting structure is formed on the isolating structure and the hard mask is exposed from the protecting structure. The exposed hard mask is removed to expose the gate.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 22, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Che-Hua HSU, Shao- Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen, Shin-Chi Chen, Hung-Ling Shih, Hung-Yi Wu, Heng-Ching Huang
  • Patent number: 8138582
    Abstract: An impurity doping system is disclosed, which includes an impurity doping device for doping an impurity into a surface of a solid state base body, a measuring device for measuring an optical characteristic of an area into which the impurity is doped, and an annealing device for annealing the area into which the impurity is doped. The impurity doping system realizes an impurity doping not to bring about a rise of a substrate temperature, and measures optically physical properties of a lattice defect generated by the impurity doping step to control such that subsequent steps are optimized.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: March 20, 2012
    Assignee: Panasonic Corporation
    Inventors: Cheng-Guo Jin, Yuichiro Sasaki, Bunji Mizuno
  • Patent number: 8129202
    Abstract: It is intended to provide a plasma doping method and apparatus which are superior in the controllability of the concentration of an impurity that is introduced into a surface layer of a sample. A prescribed gas is introduced into a vacuum container 1 from a gas supply apparatus 2 while being exhausted by a turbomolecular pump 3 as an exhaust apparatus. The pressure in the vacuum container 1 is kept at a prescribed value by a pressure regulating valve 4. High-frequency electric power of 13.56 MHz is supplied from a high-frequency power source 5 to a coil 8 disposed close to a dielectric window 7 which is opposed to a sample electrode 6, whereby induction-coupled plasma is generated in the vacuum container 1. A high-frequency power source 10 for supplying high-frequency electric power to the sample electrode 6 is provided. Every time a prescribed number of samples have been processed, a dummy sample is subjected to plasma doping and then to heating.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: March 6, 2012
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Yuichiro Sasaki, Katsumi Okashita, Hiroyuki Ito, Bunji Mizuno, Cheng-Guo Jin, Ichiro Nakayama
  • Publication number: 20120010163
    Abstract: The present invention relates to novel therapeutics with antibacterial activity, processes for their preparation, and pharmaceutical, veterinary and nutritional compositions containing them as active ingredients. The present invention also relates to uses of the novel therapeutics, for example, as medicants or food additives in the treatment of bacterial infections or to aid body mass gain in a subject.
    Type: Application
    Filed: September 17, 2010
    Publication date: January 12, 2012
    Applicant: Albany Molecular Research, Inc.
    Inventors: GRANT J. CARR, DAVID D. MANNING, ZHICAL YANG, CHENG GUO, JUN-HO MAENG, JOHN RABENSTEIN, PETER C. MICHELS, MATTHEW W. CHASE
  • Publication number: 20110294274
    Abstract: A method of forming metal gate transistor includes providing a substrate; forming a gate dielectric layer, a work function metal layer and a polysilicon layer stacked on the substrate; forming a hard mask and a patterned photoresist on the polysilicon layer; removing the patterned photoresist, and next utilizing the hard mask as an etching mask to remove parts of the polysilicon layer and parts of the work function metal layer. Thus, a gate stack is formed. Since the patterned photoresist is removed before forming the gate stack, the gate stack is protected from damages of the photoresist-removing process. The photoresist-removing process does not attack the sidewalls of the gate stack, so a bird's beak effect of the gate dielectric layer is prevent.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Inventors: Che-Hua Hsu, Shao-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen
  • Publication number: 20110237527
    Abstract: The present invention relates to compounds which are inhibitors of sodium dependent glucose co-transporter-2 (SGLT-2). These compounds are used in the treatment of various disorders, including diabetes, impaired glucose tolerance, insulin resistance, retinopathy, nephropathy, neuropathy, cataracts, hyperglycemia, hyperinsulinemia, hyperchlolesterolemia, elevated blood level of free fatty acids or glycerol, hyperlipidemia, hypertriglyceridemia, obesity, wound healing, tissue ischemia, atherosclerosis, and hypertension. These compounds and compositions are also useful for treating and preventing kidney stones, hyperuricemia, gout, and hyponatremia. Methods of making these compounds are also described in the present invention.
    Type: Application
    Filed: March 21, 2011
    Publication date: September 29, 2011
    Applicant: ALBANY MOLECULAR RESEARCH, INC.
    Inventors: Shuang LIU, Cheng GUO, Min HU, Douglas B. KITCHEN, Peter R. GUZZO, Russell DEORAZIO
  • Publication number: 20110237056
    Abstract: An object of this invention is to provide a method for making a junction which is simple in the process, high in the throughput, and can make a shallow junction with high accuracy. After the suitable state of a substrate surface adapted to the wavelength of an electromagnetic wave to be applied has been formed, the electromagnetic wave is applied to electrically activate impurities so that the excited energy is effectively absorbed within the impurity thin film, thereby effectively making a shallow junction.
    Type: Application
    Filed: June 7, 2011
    Publication date: September 29, 2011
    Applicant: Panasonic Corporation
    Inventors: Yuichiro SASAKI, Cheng-Guo JIN, Bunji MIZUNO
  • Patent number: 8003461
    Abstract: A method of fabricating an efuse structure, a resistor structure and a transistor structure. First, a work function metal layer, a polysilicon layer and a first hard mask layer are formed to cover a transistor region, a resistor region and an e-fuse region on a substrate. Then, the work function metal layer on the resistor region and the efuse region is removed by using a first photomask. Later, a gate, a resistor, an efuse are formed in the transistor region, the resistor region and the efuse region respectively. After that, a dielectric layer aligning with the top surface of the gate is formed. Later, the polysilicon layer in the gate is removed by taking a second hard mask as a mask to form a recess. Finally, a metal layer fills up the recess.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: August 23, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Che-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen, Shao-Hua Hsu
  • Publication number: 20110189827
    Abstract: A method of fabricating an efuse structure, a resistor structure and a transistor structure. First, a work function metal layer, a polysilicon layer and a first hard mask layer are formed to cover a transistor region, a resistor region and an e-fuse region on a substrate. Then, the work function metal layer on the resistor region and the efuse region is removed by using a first photomask. Later, a gate, a resistor, an efuse are formed in the transistor region, the resistor region and the efuse region respectively. After that, a dielectric layer aligning with the top surface of the gate is formed. Later, the polysilicon layer in the gate is removed by taking a second hard mask as a mask to form a recess. Finally, a metal layer fills up the recess.
    Type: Application
    Filed: February 4, 2010
    Publication date: August 4, 2011
    Inventors: Che-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen, Shao-Hua Hsu
  • Patent number: 7981779
    Abstract: An object of this invention is to provide a method for making a junction which is simple in the process, high in the throughput, and can make a shallow junction with high accuracy. After the suitable state of a substrate surface adapted to the wavelength of an electromagnetic wave to be applied has been formed, the electromagnetic wave is applied to electrically activate impurities so that the excited energy is effectively absorbed within the impurity thin film, thereby effectively making a shallow junction.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: July 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Cheng-Guo Jin, Bunji Mizuno
  • Patent number: D657787
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: April 17, 2012
    Assignee: SMART Technologies ULC
    Inventors: Mark Andrew Fletcher, Alan Peter Boykiw, Cheng Guo, Paul Anthony Auger