Abstract: An imaging system lens assembly includes a first lens group and a second lens group. The first lens group includes a first catadioptric lens element and a second catadioptric lens element, the second lens group includes at least one lens element. Each of an object-side surface and an image-side surface of the first catadioptric lens element and the second catadioptric lens element includes a central region and a peripheral region. The peripheral region of the object-side surface of the first catadioptric lens element includes a first refracting surface. The peripheral region of the image-side surface of the second catadioptric lens element includes a first reflecting surface. The central region of the object-side surface of the first catadioptric lens element includes a second reflecting surface. The central region of the image-side surface of the second catadioptric lens element includes a last refracting surface.

Abstract: A method for evaluating a risk of a subject getting a specific disease includes steps of: storing a reference database that contains original parameter sets; selecting target alleles from an SNP profile derived from genome sequencing data of a subject; selecting target parameter sets from among the original parameter sets; calculating, for each of the target parameter sets, a race factor based on a global risk allele frequency and a group-specific risk allele frequency included in the target parameter set; calculating a genetic factor based on statistics, global reference allele frequencies, the race factors for the target parameter sets, and numbers of chromosomes in homologous chromosome pairs included in the target parameter sets; calculating a citation factor based on numbers of citation times included in the target parameter sets; and calculating a risk score based on the genetic factor and the citation factor.

Abstract: Disclosed are calibration techniques that can be implemented by a device that conducts biological tests. In certain embodiments, the device for testing a biological specimen includes a receiving mechanism to receive a carrier, a camera module arranged to capture imagery of the carrier, and a processor. Some examples of the processor can detect a calibration mode trigger. In calibration mode, the processor can divide the captured imagery into segments and selectively perform one or more calibration procedures for each segment. Then, the processor records a calibration result for each segment.

Abstract: A testing apparatus for a semiconductor package includes a circuit board, testing patterns and a socket. The circuit board has a testing region and includes a plurality of testing contacts and a plurality of signal contacts distributed in the testing region. The testing patterns are embedded in the circuit board and electrically connected to the testing contacts, where each of the testing patterns includes a first conductive line and a second conductive line including a main portion and a branch portion connected to main portion. The first conductive line is connected to the main portion. The socket is located on the circuit board and comprising connectors electrically connected to the circuit board, wherein the connectors are configured to transmit electric signals for testing the semiconductor package from the testing apparatus.

Abstract: A testing apparatus for a semiconductor package includes a circuit board, testing patterns and a socket. The circuit board has a testing region and includes a plurality of testing contacts and a plurality of signal contacts distributed in the testing region. The testing patterns are embedded in the circuit board and electrically connected to the testing contacts, where each of the testing patterns includes a first conductive line and a second conductive line including a main portion and a branch portion connected to main portion. The first conductive line is connected to the main portion. The socket is located on the circuit board and comprising connectors electrically connected to the circuit board, wherein the connectors are configured to transmit electric signals for testing the semiconductor package from the testing apparatus.

Abstract: A testing apparatus for a semiconductor package includes a circuit board, testing patterns and a socket. The circuit board has a testing region and includes a plurality of testing contacts and a plurality of signal contacts distributed in the testing region. The testing patterns are embedded in the circuit board and electrically connected to the testing contacts, where each of the testing patterns includes a first conductive line and a second conductive line including a main portion and a branch portion connected to main portion. The first conductive line is connected to the main portion. The socket is located on the circuit board and comprising connectors electrically connected to the circuit board, wherein the connectors are configured to transmit electric signals for testing the semiconductor package from the testing apparatus.

Abstract: A pixel structure includes a light-emitting module, multiple sub-pixel circuits, and an internal driving circuit. The light-emitting module includes multiple sub-pixel light-emitting elements, and is disposed on a first plane. The multiple sub-pixel circuits are disposed on a second plane, and each of the multiple sub-pixel circuits is electrically connected with a corresponding one of the multiple sub-pixel light-emitting elements. The internal driving circuit is disposed on the second plane, and is electrically connected with one of the multiple sub-pixel circuits. The first plane is different from the second plane, and the multiple sub-pixel circuits and the internal driving circuit are located in a vertical projection projected by the light-emitting module onto the second plane.

Abstract: A pixel structure includes a light-emitting module, multiple sub-pixel circuits, and an internal driving circuit. The light-emitting module includes multiple sub-pixel light-emitting elements, and is disposed on a first plane. The multiple sub-pixel circuits are disposed on a second plane, and each of the multiple sub-pixel circuits is electrically connected with a corresponding one of the multiple sub-pixel light-emitting elements. The internal driving circuit is disposed on the second plane, and is electrically connected with one of the multiple sub-pixel circuits. The first plane is different from the second plane, and the multiple sub-pixel circuits and the internal driving circuit are located in a vertical projection projected by the light-emitting module onto the second plane.

Abstract: A shift register circuit and a gate driver including the shift register circuit. The shift register circuit includes an input circuit, a drive circuit, a pull-down circuit, a regulator circuit and a pull-up circuit. The input circuit is configured to receive a first clock signal and is coupled to the first node. The driving circuit is configured to receive the first clock signal and a second clock signal. The input circuit is coupled to the first node. The pull-down circuit is configured to receive the voltage of the first node. The pull-down circuit is coupled to the first node and an output terminal. The pull-down circuit outputs the first voltage to the output terminal in response to the voltage of the first node.

Abstract: A pixel driving circuit utilizing a transistor having two gate ends as the driving unit for pixels of a display panel to provide a stable driving current to compensate for the variation of threshold voltages of transistors in different pixels and to improve the uniformity of the brightness of the display panel.

Abstract: A pixel structure includes a first TFT, an adhesive layer, an LED, and a detection conductive layer. The first TFT is coupled to a conductive layer and is configured to transmit display data to the conductive layer. The adhesive layer covers the conductive layer. The LED is disposed on the adhesive layer. The detection conductive layer is disposed on the adhesive layer, and the detection conductive layer, the adhesive layer, and the conductive layer constitute a detection capacitor. Here, a thickness of the detection conductive layer is equal to or slightly greater than a height of the LED.

Abstract: A shift register circuit and a gate driver including the shift register circuit. The shift register circuit includes an input circuit, a drive circuit, a pull-down circuit, a regulator circuit and a pull-up circuit. The input circuit is configured to receive a first clock signal and is coupled to the first node. The driving circuit is configured to receive the first clock signal and a second clock signal. The input circuit is coupled to the first node. The pull-down circuit is configured to receive the voltage of the first node. The pull-down circuit is coupled to the first node and an output terminal. The pull-down circuit outputs the first voltage to the output terminal in response to the voltage of the first node.

Abstract: A pixel driving circuit includes a driving unit receiving a first control signal via a first control end, and the driving unit is biased according to the first control signal to provide a driving current to a light emitting element. One end of a capacitor is connected to a second control end of the driving unit, and the other end of the capacitor is connected to a first end or a second end of the driving unit. A compensation unit receives a second control signal via a first control end, and the compensation unit is biased according to the second control signal. A first switch unit receives a third control signal via a control end, and thereby the first switch unit is turned on. A second switch unit receives a fourth control signal via a control end, and thereby the second switch unit is turned on.

Abstract: A display device has a substrate for disposing a display area having an array of pixels, and control circuits having shift registers and latches to provide image data and timing control signals to the pixels. The control circuits have signal lines electrically connected to a connection cable to receive therefrom data signals indicative of the image data and timing pulses indicative of the timing control signals. The connection cable is also configured to provide reference signals to the shift registers and latches in the control circuits. The data signals are digital signals having an amplitude range greater than the amplitude range of the reference signals. No driver IC is disposed on the substrate to process analog signals. Each of the pixels has three sub-pixels and each of the color sub-pixels has three color sub-areas configured to receive timing control signals from a different scan line.

Abstract: A smart zipper includes a zipper, a voltage generator, a voltage detector, and a processor. The zipper includes a first left tooth and a first right tooth. The first left tooth is electrically connected to a first left wire and is supplied with a supply voltage. The first right tooth is electrically connected to a first right wire. The voltage generator generates the supply voltage. The voltage detector detects the voltage of the first right wire to generate a first detection signal. The processor determines first coupling information about whether the first left tooth is electrically connected to the first right tooth, according to the first detection signal.

Abstract: A pixel structure includes a first TFT, an adhesive layer, an LED, and a detection conductive layer. The first TFT is coupled to a conductive layer and is configured to transmit display data to the conductive layer. The adhesive layer covers the conductive layer. The LED is disposed on the adhesive layer. The detection conductive layer is disposed on the adhesive layer, and the detection conductive layer, the adhesive layer, and the conductive layer constitute a detection capacitor. Here, a thickness of the detection conductive layer is equal to or slightly greater than a height of the LED.

Abstract: A display panel and a compensation circuit are provided. The display panel has a periphery region and a display region. The display panel includes pixel columns and a threshold voltage compensation circuit. The pixel columns are disposed in the display region. The threshold voltage compensation circuit is disposed in the periphery region. The threshold voltage compensation circuit receives a compensation voltage, outputs threshold voltage information of a compensation transistor based on the compensation voltage, and generates compensated display data based on the threshold voltage information and display data.

Abstract: A display panel and a compensation circuit are provided. The display panel has a periphery region and a display region. The display panel includes pixel columns and a threshold voltage compensation circuit. The pixel columns are disposed in the display region. The threshold voltage compensation circuit is disposed in the periphery region. The threshold voltage compensation circuit receives a compensation voltage, outputs threshold voltage information of a compensation transistor based on the compensation voltage, and generates compensated display data based on the threshold voltage information and display data.