Abstract: A method of forming a field oxide isolation region is described, in which a masking layer is formed over a silicon substrate. The masking layer is patterned to form an opening for the field oxide isolation region, whereby the remainder of the masking layer forms an implant mask. A conductivity-imparting dopant is implanted through the opening into the silicon substrate. Oxygen is implanted through the opening into the silicon substrate in multiple implantation steps. The implant mask is removed. The field oxide isolation region is formed in and on the silicon substrate, by annealing in a non-oxygen ambient. Alternately, the field oxide isolation region is formed by annealing in oxygen, simultaneously forming a gate oxide in the region between the field oxide isolation regions.

Abstract: The invention provides a diagnostic method of determining Rh genotypes by the identification of the molecular basis of Rh polymorphisms. Specifically, the invention provides a method for directly determining Dd and associated CcEe genotypes with great accuracy, overcoming problems associated with traditional serologic typing methods and leading to a direct discrimination of D/D, D/d, and d/d genetic status. The diagnostic method allows genotyping of fetuses to assess the risk of hemolytic diseases caused by Rh alloimmunization and genetic counseling and/or testing of couples to predict the outcome of pregnancies in relation to Rh incompatibilities. The method of the invention preferably employs amplification of Rh nucleic acid sequences, and employs differential cleavage of RhD-, RhCc- and/or RhEe-specific nucleic acid sequences by a restriction enzyme. Furthermore, diagnostic kits for the determination of Rh genotypes are provided.

Abstract: A new method of fabricating a polycide gate is described. A gate polysilicon layer is provided a gate oxide layer on the surface of a substrate. A thin conducting diffusion barrier is deposited overlying the gate polysilicon layer. A of tungsten silicide is deposited overlying the thin diffusion barrier layer wherein a reaction gas in the deposition contains fluorine atoms and wherein fluorine atoms are incorporated into the tungsten layer. The gate polysilicon, thin conducting barrier, and tungsten silicide layers are patterned form the polycide gate structures. The wafer is annealed complete formation of the polycide gate structures wherein number of fluorine atoms from the tungsten silicide layer into the gate polysilicon layer are minimized by presence of the thin conducting diffusion barrier layer wherein because the diffusion of the fluorine atoms is the thickness of the gate oxide layer does not This prevents the device from degradation such as voltage shift and saturation current descrease.

Abstract: A new isolation technology fabrication process is provided including the step of forming a trench in a semiconductor material. Then, several poly walls are formed in the trench. The poly walls are oxidized to form a single oxide isolation region filling the trench.

Abstract: A MOS capacitor structure in accordance with the invention is formed by depositing a polysilicon electrode layer on the substrate. Oxide regions are then formed on the polysilicon layer. Using the oxide regions as a mask, pillars are etched in the polysilicon electrode layer.

Abstract: A capacitor structure suitable for use in Dynamic Random Access Memory (DRAM) Integrated Circuit (IC) devices and its method of fabrication is disclosed. The capacitor includes a main or root trench extending vertically into the silicon substrate and at least one buried trench extending horizontally into the side wall of the main trench. The enlarged trench sidewall surface area as a result of the added buried trenches increases the total capacitance of the capacitor and it suitable for use with high density, high data volume memory devices. The buried trenches are formed by implanting oxygen or nitrogen ions into the designated depths of the silicon substrate, subsequently annealing the entire substrate at the absence of gaseous oxygen, and etching away the converted silicon dioxide or silicon nitride. The formed trench system can reduce the accumulation of the structural stress to avoid the formation of crystalline defects and obtain the resulting device with better quality.

Abstract: A method is described for forming a dynamic random access memory cell capacitor in which polysilicon word lines are formed in a self-aligned method on top of the gate electrodes of the memory cell wherein the polysilicon word lines act to increase the surface area and hence to increase the capacitance of the capacitor.

Abstract: A process of fabricating a read only memory device (ROM) wherein the buried N+lines have desirable well defined very narrow widths and are closely spaced. In the process, an insulating layer is deposited on the substrate. Openings for the buried N+lines having vertical sidewalls are formed through the insulating layer. Spacer layers are formed on the vertical sidewalls of the openings. Impurities are implanted through the openings. The insulating layers is removed and the substrate is oxidized to form silicon oxide insulation strips over the buried N+implanted regions. Next, the read only memory (ROM) device is completed by fabricating floating gates and overlying control gates between the buried N+lines interconnected by a conductive lines that are orthogonal to the buried N+buried lines.

Abstract: A method of metallization using a tungsten plug is described. A contact hole is opened to the semiconductor substrate through an insulating layer covering semiconductor structures in and on the semiconductor substrate. A glue layer is deposited conformally over the surface of the insulating layer and within the contact opening. A tungsten plug is formed within the contact opening. The glue layer is removed except for portions of the glue layer underneath the tungsten plug and on the lower sides of the tungsten plug. Ditches are left on the upper sides of the tungsten plug where the glue layer has been removed. The ditches around the tungsten plug are filled with a dielectric material. A second metallization is deposited and patterned. The patterned second metallization does not extend over one side portion of the tungsten plug; that is, there is no dog-bone formation.

Abstract: A new method of fabricating a polycide gate structure is described. A gate polysilicon layer is provided overlying a gate oxide layer on the surface of a semiconductor substrate. A thin conducting diffusion barrier layer is deposited overlying the gate polysilicon layer. A layer of tungsten silicide is deposited overlying the thin conducting diffusion barrier layer wherein a reaction gas used in the deposition contains fluorine atoms and wherein the fluorine atoms are incorporated into the tungsten silicide layer. The gate polysilicon, thin conducting diffusion barrier, and tungsten silicide layers are patterned to form the polycide gate structures.

Abstract: A method for manufacturing a self-aligned contact MOS field effect transistor integrated circuit has a substrate doped with a first conductivity. The substrate has field oxide regions separating the planned active transistor regions, and gate dielectric/gate electrode structures over the designated channel regions for the integrated circuit device. Opposite type conductivity ions are implanted into the doped silicon substrate to form the lightly doped portion of the source/drain regions for the transistor. Dielectric spacers are formed on the sidewalls of the dielectric/gate electrode structures. A block out mask is formed over the source/drain regions designated to have self-aligned contacts made thereto. Opposite type conductivity ions are implanted into the substrate to form heavily doped portions to complete the formation of the source/drain regions in those nondesignated self-aligned contact regions. The block out mask is removed.