Abstract: A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer.

Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.

Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.

Abstract: A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer.

Abstract: Compounds for use in prevention and/or treatment of pain are disclosed. The compounds are derived by conjugation of N6-(4-hydroxybenzyl)adenosine and analogous compounds with amino acids or peptides. In one embodiment of the invention, the compound is 5?-glycylcarbonyl-N6-(4-hydroxybenzyl)adenosine (I-a1). In another embodiment of the invention, the compound is 5?-deoxy-5?-(N?-glycylureido)-N6-(4-hydroxybenzyl)adenosine (I-d1). Also disclosed are methods of making and using the same.

Abstract: A process for manufacturing a semiconductor device and the resulting structure are presented. In an embodiment a source/drain region is grown. Once grown, the source/drain region is reshaped in order to remove facets. The reshaping may be performed using an etching process whereby a lateral etch rate of the source/drain region is larger than a vertical etch rate of the source/drain region.

Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

Abstract: A structure includes a stepped crystalline substrate that includes an upper step, a lower step, and a step rise. A first fin includes a crystalline structure having a first lattice constant. The first fin is formed over the lower step. A second fin includes a crystalline structure having a second lattice constant, the second lattice constant being different than the first lattice constant. The second fin can be formed over the upper step apart from the first fin. A second crystalline structure can be formed over the first crystalline structure and the tops of the fins aligned. The first and second fins can be made of the same material, but with different heights and different channel strain values. The first fin can be used as an NMOS fin and the second fin can be used as a PMOS fin of a CMOS FinFET.

Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.

Abstract: A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer.

Abstract: An antenna structure includes a metal housing, a switching circuit, and a first feed source. The metal housing includes a front frame, a backboard, and a side frame. The side frame defines a slot and the front frame defines a groove. A first portion of the front frame positioned at a first side of the groove forms a first branch. A second portion of the front frame extending from a second side of the groove to one end of the slot forms a second branch. The first feed source is electrically connected to the first branch and the second branch, and the first branch is grounded through the switching circuit.

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

Abstract: An antenna structure includes a metallic member and a first feed source. The metallic member includes a front frame, a backboard, and a side frame. The side frame is positioned between the front frame and the backboard. The first feed source is electrically connected to the front frame. The side frame includes at least a top portion, a first side portion, and a second side portion. The first side portion and the second side portion are respectively connected to two ends of the top portion. The side frame defines a slot and the slot is defined on the top portion. The front frame defines a gap. The gap communicates with the slot and extends across the front frame.

Abstract: A touch sensitive processing apparatus includes: a driving circuit for connecting to multiple first electrodes, respectively; a sensing circuit for connecting to multiple second electrodes, respectively; and a processor configured for executing multiple sets of first round mutual capacitive detecting steps. Each set of the first round mutual capacitive detecting step further includes: having the driving circuit sending a driving signal to neighboring N first electrodes, where N is a positive integer larger than 1; and having the sensing circuit simultaneously detecting the driving signal via the second electrodes for generating multiple first round sensing information with respective to the set of first round mutual capacitive detecting step. Each of the first round sensing information corresponds to an intersection of central line of the N first electrodes and the second electrode.

Abstract: A capacitive touch panel includes a substrate having a touch sensing layer on the surface thereof, and an electrode module mounted in the touch sensing layer and including first electrodes arranged in parallel in X-axis direction and second electrodes arranged in parallel in Y-axis direction. Each first electrode includes multiple first electrode elements and multiple first signal lines arranged in X-axis direction and respectively electrically connected between each two adjacent first electrode elements. Each second electrode includes multiple second electrode elements respectively disposed adjacent to and spaced from the first electrode elements of one respective first electrode and multiple second signal lines arranged in Y-axis direction and respectively electrically connected between each two adjacent second electrode elements. Thus, the electrode module accurately senses the touch signal of the touch sensing layer without distortion.

Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

Abstract: An antenna structure includes a metal housing, a first feed source, a first ground portion, and a first switching circuit. The metal housing includes a front frame, a backboard, and a side frame. The side frame defines a slot and the front frame defines a first gap and a second gap. The metal housing is divided into at least a first portion by the slot, the first gap, and the second gap. The first feed source is electrically connected to the first portion for supplying current to the first portion. The first ground portion is electrically connected to the first portion for grounding the first portion. One end of the first switching circuit is electrically connected to the first portion. Another end of the first switching circuit is grounded.

Abstract: An antenna structure includes a housing, a first feed source, and a second feed source. The first feed source is electrically coupled to a first radiating portion of the housing and adapted to provide an electric current to the first radiating portion. The second feed source is electrically coupled to one of a second radiating portion or a third radiating portion of the housing. The other one of the second radiating portion or the third radiating portion is electrically coupled to the first radiating portion.

Abstract: An antenna structure includes a housing, a first feed source, and a second feed source. The first feed source is electrically coupled to a first radiating portion of the housing and adapted to provide an electric current to the first radiating portion. The second feed source is electrically coupled to one of a second radiating portion or a third radiating portion of the housing. The other one of the second radiating portion or the third radiating portion is electrically coupled to the first radiating portion.