Abstract: An antenna structure includes a housing and a first feed source. The first feed source is electrically coupled to a first radiating portion of the housing and adapted to provide an electric current to the first radiating portion.

Abstract: An antenna structure includes a housing, a first feed source, a second feed source, a third feed source, and a radiating body. The first feed source is electrically coupled to a first radiating portion of the housing and adapted to provide an electric current to the first radiating portion. The second feed source is electrically coupled to the second radiating portion and adapted to provide an electric current to the second radiating portion. The radiating body is mounted within the housing and electrically coupled to the third feed source. The third feed source provides an electric current to the radiating body.

Abstract: A controller for position detection is disclosed. At least one first 1-D position corresponding to at least one external object is determined based on signals of a plurality of first sensors by self-capacitance detection. Then, at least one second 1-D position corresponding to the at least one first 1-D position is determined based on signals of a plurality of second sensors by mutual-capacitance detection, wherein each second 1-D position is determined based on a differential sensing information whose each value is based on signals of two second sensors by mutual-capacitance detection.

Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

Abstract: The present disclosure describes an exemplary fabrication method of a p-type fully strained channel that can suppress the formation of {111} facets during a silicon germanium epitaxial growth. The exemplary method includes the formation of silicon epitaxial layer on a top, carbon-doped region of an n-type region. A recess is formed in the silicon epitaxial layer via etching, where the recess exposes the top, carbon-doped region of the n-type region. A silicon seed layer is grown in the recess, and a silicon germanium layer is subsequently epitaxially grown on the silicon seed layer to fill the recess. The silicon seed layer can suppress the formation of growth defects such as, for example, {111} facets, during the silicon germanium epitaxial layer growth.

Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.

Abstract: Semiconductor structures and method for forming the same are provide. The method includes forming a gate structure over a substrate and forming a recess in the substrate adjacent to the gate structure. The method further includes forming a doped region at a sidewall and a bottom surface of the recess and partially removing the doped region to modify a shape of the recess. The method further includes forming a source/drain structure over a remaining portion of the doped region.

Abstract: An antenna structure includes a metal housing, a first feed source, and a first radiator. The metal housing includes a front frame, a backboard, and a side frame. The side frame defines a slot and the front frame defines a gap. The metal housing is divided into at least a long portion and a short portion by the slot and the gap. The radiator is positioned in the housing and includes a first radiating portion and a second radiating portion. One end of the first radiating portion is electrically connected to the first feed source and another end of the first radiating portion is spaced apart from the long portion. One end of the second radiating portion is electrically connected to the first feed source and another end of the second radiating portion is spaced apart from the short portion.

Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.

Abstract: A process for manufacturing a semiconductor device and the resulting structure are presented. In an embodiment a source/drain region is grown. Once grown, the source/drain region is reshaped in order to remove facets. The reshaping may be performed using an etching process whereby a lateral etch rate of the source/drain region is larger than a vertical etch rate of the source/drain region.

Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.

Abstract: A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer.

Abstract: A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer.

Abstract: An antenna structure includes a metallic member, a first radiator, and an isolating portion. The metallic member includes a front frame, a backboard, and a side frame. The side frame includes at least a top portion, a first side portion, and a second side portion. The isolating portion is electrically connected to the first radiator. The side frame defines a slot and the slot is defined on the top portion. The front frame defines a gap. The gap communicates with the slot and extends across the front frame. The first portion of the front frame from a first side of the gap to a first end of the slot forms a short portion. The first radiator is positioned adjacent to the short portion and the isolation portion improves isolation between the short portion and the first radiator.

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain structure near the gate structure. The source/drain structure has an inner portion and an outer portion surrounding an entirety of the inner portion. The inner portion has a greater average dopant concentration than that of the outer portion.

Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.

Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.

Abstract: The method and device for analyzing position are disclosed. By analyzing sensing information with at least one zero-crossing, each position can be analyzed. The number of analyzed positions may be different from the number of zero-crossings. When the number of analyzed positions is different from the number of zero-crossing, the number of analyzed positions is more than one.