Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain structure near the gate structure. The source/drain structure has an inner portion and an outer portion surrounding an entirety of the inner portion. The inner portion has a greater average dopant concentration than that of the outer portion.

Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.

Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.

Abstract: The method and device for analyzing position are disclosed. By analyzing sensing information with at least one zero-crossing, each position can be analyzed. The number of analyzed positions may be different from the number of zero-crossings. When the number of analyzed positions is different from the number of zero-crossing, the number of analyzed positions is more than one.

Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain structure near the gate structure. The source/drain structure has an inner portion and an outer portion surrounding an entirety of the inner portion. The inner portion has a greater average dopant concentration than that of the outer portion.

Abstract: The method and device for position detection are disclosed. Corresponding to a first touch related sensing information, a second touch related sensing information is acquired for determining at least one position. Each position is used separately for determining the position of a centroid according to the first touch related sensing information or the second touch related sensing information.

Abstract: A controller for position detection is disclosed. At least one first 1-D position corresponding to at least one external object is determined based on signals of a plurality of first sensors by self-capacitance detection. Then, at least one second 1-D position corresponding to the at least one first 1-D position is determined based on signals of a plurality of second sensors by mutual-capacitance detection, wherein each second 1-D position is determined based on a differential sensing information whose each value is based on signals of two second sensors by mutual-capacitance detection.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a first source portion and a first drain portion over the substrate, and a first semiconductor nanowire over the substrate and between the first source portion and the first drain portion. The first semiconductor nanowire includes a first portion over the substrate and a second portion over the first portion, and the first portion has a first width, and the second portion has a second width, and the second width is less than the first width. The semiconductor device structure also includes a first gate structure over the second portion of the first semiconductor nanowire.

Abstract: Structures of a semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, and a first recess and a second recess in the substrate and at opposite sides of the gate structure. The semiconductor device also includes two source/drain structures over the first recess and the second recess respectively. At least one of the source/drain structures includes a first doped region partially filling in the first recess, a second doped region over the first doped region, and a third doped region over the second doped region. The second doped region contains more dopants than the first doped region or the third doped region.

Abstract: An antenna structure includes a metal housing, a first feed source, and a first switching circuit. The metal housing includes a front frame, a backboard, and a side frame. The side frame defines a slot and the front frame defines a first gap and a second gap. The metal housing is divided into at least a first branch and a second branch by the slot, the first gap, and the second gap. The first feed source is electrically connected to the first branch. One end of the first switching circuit is electrically connected to the first branch. Another end of the first switching circuit is grounded.

Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.

Abstract: A method includes forming a first fin and a second fin over a substrate, depositing an isolation material surrounding the first and second fins, forming a gate structure along sidewalls and over upper surfaces of the first and second fins, recessing the first and second fins outside of the gate structure to form a first recess in the first fin and a second recess in the second fin, epitaxially growing a first source/drain material protruding from the first and second recesses, and epitaxially growing a second source/drain material on the first source/drain material, wherein the second source/drain material grows at a slower rate on outermost surfaces of opposite ends of the first source/drain material than on surfaces of the first source/drain material between the opposite ends of the first source/drain material, and wherein the second source/drain material has a higher doping concentration than the first source/drain material.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a first source portion and a first drain portion over the substrate, and a first semiconductor nanowire over the substrate and between the first source portion and the first drain portion. The first semiconductor nanowire includes a first portion over the substrate and a second portion over the first portion, and the first portion has a first width, and the second portion has a second width, and the second width is less than the first width. The semiconductor device structure also includes a first gate structure over the second portion of the first semiconductor nanowire.

Abstract: A process for manufacturing a semiconductor device and the resulting structure are presented. In an embodiment a source/drain region is grown. Once grown, the source/drain region is reshaped in order to remove facets. The reshaping may be performed using an etching process whereby a lateral etch rate of the source/drain region is larger than a vertical etch rate of the source/drain region.

Abstract: A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer.

Abstract: A controller for position detection is disclosed. At least one first 1-D position corresponding to at least one external object is determined based on signals of a plurality of first sensors by self-capacitance detection. Each first 1-D position is determined based on a differential sensing information whose each value is based on signals of two first sensors by self-capacitance detection. Then, at least one second 1-D position corresponding to the at least one first 1-D position is determined based on signals of a plurality of second sensors by mutual-capacitance detection.

Abstract: A touch sensitive processing apparatus is used to detect at least one object approximating or touching a touch screen. The touch screen includes: multiple neighboring first electrodes and multiple neighboring second electrodes which are parallel to a first axis; and multiple neighboring third electrodes and multiple neighboring fourth electrodes which are parallel to a second axis. Each of the first electrodes intersects with the third electrodes to form multiple intersection areas, each of the second electrodes intersects with the fourth electrodes to form multiple intersection areas.

Abstract: A touch sensitive processing apparatus includes: a driving circuit for connecting to multiple first electrodes, respectively; a sensing circuit for connecting to multiple second electrodes, respectively; and a processor configured for executing multiple sets of first round mutual capacitive detecting steps. Each set of the first round mutual capacitive detecting step further includes: having the driving circuit sending a driving signal to neighboring N first electrodes, where N is a positive integer larger than 1; and having the sensing circuit simultaneously detecting the driving signal via the second electrodes for generating multiple first round sensing information with respective to the set of first round mutual capacitive detecting step. Each of the first round sensing information corresponds to an intersection of central line of the N first electrodes and the second electrode.

Abstract: A touch sensitive processing apparatus is used to detect at least one object approximating or touching a touch screen and is configured for iteratively executing the following steps: having a driving circuit simultaneously sending a driving signal to two or more first electrodes, wherein at least one of the two or more first electrodes intersects with multiple second electrodes to form multiple intersection areas, the other of the two or more first electrodes intersects with multiple third electrodes to form multiple intersection areas; and having a sensing circuit simultaneously sensing the driving signal via the second electrodes to generate a one-dimensional sensing information and having the sensing circuit simultaneously sensing the driving signal via the third electrodes to generate another one-dimensional sensing information.

Abstract: A touch panel includes: multiple first electrodes parallel to a first axis; multiple second electrodes parallel to a second axis; and multiple third electrodes parallel to the second axis. Each of the first electrodes is arranged to be spanned on the touch panel and intersects with the multiple second electrodes or the multiple third electrodes to form multiple intersection areas.