Patents by Inventor Cheng-Hsiung Kuo
Cheng-Hsiung Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7348832Abstract: A voltage generation system for generating operating voltages for memory devices, especially non-volatile memories, from a single external high voltage source. In one embodiment, the system comprises an input terminal for receiving an external voltage, a charge pump for producing a first high voltage based on the external voltage to be higher than the external voltage, a first regulating circuit for regulating the first high voltage to a lower predetermined voltage, a second regulating circuit for generating a second high voltage based on the external voltage to be lower than the external voltage.Type: GrantFiled: March 20, 2006Date of Patent: March 25, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiang-Tai Lu, Cheng-Hsiung Kuo, Yue-Der Chih
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Publication number: 20080024164Abstract: A system is disclosed for constructing a reconfigurable programmable logic device (PLD) comprising a first P-channel nonvolatile memory cell with a first source, a first drain and a first gate coupled to a first input node, a second P-channel nonvolatile memory cell with a second source, a second drain and a second gate coupled to a second input node, and an NMOS transistor with a third source and a third drain, wherein the first and second sources are commonly connected to a positive voltage supply (Vcc), the first, second and third drains are commonly connected to an output node and the third source is coupled to a complementary low voltage supply (Vss).Type: ApplicationFiled: July 31, 2006Publication date: January 31, 2008Inventors: Hsiang-Tai Lu, Cheng-Hsiung Kuo, Yue-Der Chih
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Publication number: 20070296022Abstract: A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.Type: ApplicationFiled: August 30, 2007Publication date: December 27, 2007Inventors: Hsiang-Tai Lu, Cheng-Hsiung Kuo, Chin-Huang Wang
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Patent number: 7282410Abstract: A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.Type: GrantFiled: July 21, 2004Date of Patent: October 16, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Tai Lu, Cheng-Hsiung Kuo, Chin-Huang Wang
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Publication number: 20070216471Abstract: A voltage generation system for generating operating voltages for memory devices, especially non-volatile memories, from a single external high voltage source. In one embodiment, the system comprises an input terminal for receiving an external voltage, a charge pump for producing a first high voltage based on the external voltage to be higher than the external voltage, a first regulating circuit for regulating the first high voltage to a lower predetermined voltage, a second regulating circuit for generating a second high voltage based on the external voltage to be lower than the external voltage.Type: ApplicationFiled: March 20, 2006Publication date: September 20, 2007Inventors: Hsiang-Tai Lu, Cheng-Hsiung Kuo, Yue-Der Chih
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Publication number: 20070155092Abstract: A method for forming a tip is disclosed. A layer is formed overlying a substrate. A mask layer is formed overlying the layer. The mask is patterned to form a mask pattern comprising an inner portion and an outer portion, wherein the inner portion is surrounded by the outer portion. The layer uncovered by the mask pattern is treated to form a reaction mask, wherein at least one portion of the reaction mask connect to form a tip of the layer under the inner portion of the mask pattern.Type: ApplicationFiled: December 29, 2005Publication date: July 5, 2007Inventors: Hsiang-Tai Lu, Cheng-Hsiung Kuo, Yue-Der Chih
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Patent number: 7158414Abstract: A reference voltage generator circuit for nonvolatile memory devices is disclosed. The circuit has at least one sense amplifier bias reference voltage generator (SABRVG) for generating a reference voltage at a predetermined reference point that is coupled to a start-up bias reference voltage generator (SBRVG). It also includes a monitor reference voltage generator (MRVG) for generating a monitor reference voltage, and a comparison module for comparing the monitor reference voltage with the reference voltage to produce a start-up control signal, wherein the SBRVG enhances a changing speed of the reference voltage during a reading cycle of the nonvolatile memory and when the monitor reference and the reference voltages are matched, the start-up control signal stops the SBRVG from operating, thereby having the SABRVG maintain the reference voltage.Type: GrantFiled: December 30, 2004Date of Patent: January 2, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Cheng-Hsiung Kuo
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Patent number: 7064985Abstract: A source line driver for a flash memory includes a plurality of source driving units and a control circuit to drive a plurality of source lines. Each source line is coupled to memory cells in a row. Each source driving unit drives the corresponding source line and is coupled to the control circuit at a common node. The control circuit is coupled between the common node. The control circuit is coupled between the common node and a ground line. When any memory cell is assigned to execute a program operation, the control circuit isolates the common node and the ground. When the memory cells are not assigned to execute the program operation, the control circuit couples the common node to the ground line.Type: GrantFiled: May 27, 2004Date of Patent: June 20, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Cheng-Hsiung Kuo
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Patent number: 7016233Abstract: A wordline decoder for a memory device drives a word line of a memory array and comprises a first circuit, a second circuit, and a buffer circuit. The first circuit receives voltage from a first voltage source. The second circuit receives voltage from a second voltage source. During an erase cycle, the buffer circuit receives a third voltage higher than the second voltage and lower than the first voltage. During read and program cycles, the buffer circuit receives a fourth voltage substantially equal to the first and second voltage.Type: GrantFiled: May 17, 2004Date of Patent: March 21, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Cheng-Hsiung Kuo
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Patent number: 7002861Abstract: An improved memory device and the method for programming the same are disclosed. The memory device includes at least one memory block requiring a word line pre-charge time to be long enough to program one or more selected memory cells. A monitoring circuit is added for detecting one or more word lines to reach a predetermined threshold voltage to enable a predetermined high voltage to be supplied to one or more latches of the memory cells.Type: GrantFiled: April 16, 2004Date of Patent: February 21, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Cheng-Hsiung Kuo
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Publication number: 20060019444Abstract: A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.Type: ApplicationFiled: July 21, 2004Publication date: January 26, 2006Inventors: Hsiang-Tai Lu, Cheng-Hsiung Kuo, Chin-Huang Wang
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Patent number: 6980047Abstract: A circuit, and a method, provide low power high voltage ramp-up control for on-chip semiconductor power supplies, efficiently generating on-chip high voltage to support programming of electrically erasable programmable read only memories, EEPROMs or flash memory. The on-chip efficiency is achieved by eliminating output leakage. In addition, a feedback-controlled transistor is utilized to slow down the frequency required from a current controlled oscillator stage, and to provide the on-chip high voltage with low power dissipation.Type: GrantFiled: June 20, 2002Date of Patent: December 27, 2005Assignee: Taiwan Semiconductor Manufacturing CompanyInventor: Cheng-Hsiung Kuo
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Publication number: 20050265085Abstract: A source line driver is provided. The source line driver for a flash memory includes a plurality of source driving units and a control circuit to drive a plurality of source lines. Each source line is coupled to memory cells in a row. Each source driving unit drives the corresponding source line and is coupled to the control circuit at a common node. The control circuit is coupled between the common node and a ground line. When any memory cell is assigned to execute a program operation, the control circuit isolates the common node and the ground. When the memory cells are not assigned to execute the program operation, the control circuit couples the common node to the ground line.Type: ApplicationFiled: May 27, 2004Publication date: December 1, 2005Inventor: Cheng-Hsiung Kuo
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Publication number: 20050259471Abstract: A reference voltage generator circuit for nonvolatile memory devices is disclosed. The circuit has at least one sense amplifier bias reference voltage generator (SABRVG) for generating a reference voltage at a predetermined reference point that is coupled to a start-up bias reference voltage generator (SBRVG). It also includes a monitor reference voltage generator (MRVG) for generating a monitor reference voltage, and a comparison module for comparing the monitor reference voltage with the reference voltage to produce a start-up control signal, wherein the SBRVG enhances a changing speed of the reference voltage during a reading cycle of the nonvolatile memory and when the monitor reference and the reference voltages are matched, the start-up control signal stops the SBRVG from operating, thereby having the SABRVG maintain the reference voltage.Type: ApplicationFiled: May 19, 2004Publication date: November 24, 2005Inventor: Cheng-Hsiung Kuo
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Publication number: 20050259470Abstract: A reference voltage generator circuit for nonvolatile memory devices is disclosed. The circuit has at least one sense amplifier bias reference voltage generator (SABRVG) for generating a reference voltage at a predetermined reference point that is coupled to a start-up bias reference voltage generator (SBRVG). It also includes a monitor reference voltage generator (MRVG) for generating a monitor reference voltage, and a comparison module for comparing the monitor reference voltage with the reference voltage to produce a start-up control signal, wherein the SBRVG enhances a changing speed of the reference voltage during a reading cycle of the nonvolatile memory and when the monitor reference and the reference voltages are matched, the start-up control signal stops the SBRVG from operating, thereby having the SABRVG maintain the reference voltage.Type: ApplicationFiled: December 30, 2004Publication date: November 24, 2005Inventor: Cheng-Hsiung Kuo
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Patent number: 6967871Abstract: A reference voltage generator circuit for nonvolatile memory devices is disclosed. The circuit has at least one sense amplifier bias reference voltage generator (SABRVG) for generating a reference voltage at a predetermined reference point that is coupled to a start-up bias reference voltage generator (SBRVG). It also includes a monitor reference voltage generator (MRVG) for generating a monitor reference voltage, and a comparison module for comparing the monitor reference voltage with the reference voltage to produce a start-up control signal, wherein the SBRVG enhances a changing speed of the reference voltage during a reading cycle of the nonvolatile memory and when the monitor reference and the reference voltages are matched, the start-up control signal stops the SBRVG from operating, thereby having the SABRVG maintain the reference voltage.Type: GrantFiled: May 19, 2004Date of Patent: November 22, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Cheng-Hsiung Kuo
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Publication number: 20050254331Abstract: A wordline decoder for a memory device drives a word line of a memory array and comprises a first circuit, a second circuit, and a buffer circuit. The first circuit receives voltage from a first voltage source. The second circuit receives voltage from a second voltage source. During an erase cycle, the buffer circuit receives a third voltage higher than the second voltage and lower than the first voltage. During read and program cycles, the buffer circuit receives a fourth voltage substantially equal to the first and second voltage.Type: ApplicationFiled: May 17, 2004Publication date: November 17, 2005Inventor: Cheng-Hsiung Kuo
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Publication number: 20050232048Abstract: An improved memory device and the method for programming the same are disclosed. The memory device includes at least one memory block requiring a word line pre-charge time to be long enough to program one or more selected memory cells. A monitoring circuit is added for detecting one or more word lines to reach a predetermined threshold voltage to enable a predetermined high voltage to be supplied to one or more latches of the memory cells.Type: ApplicationFiled: April 16, 2004Publication date: October 20, 2005Inventor: Cheng-Hsiung Kuo
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Publication number: 20050132315Abstract: Within both a method for revising a patterned conductor layer and a system for revising the patterned conductor layer there is provided within each wiring layout record within a series of wiring layout records within a wiring layout database directed towards a series of microelectronic fabrications an unoccupied equivalent wiring location within which may be formed at least one optional wiring pattern. When there is designed within an unoccupied equivalent wiring location for a single wiring layout record within the series of wiring layout records at least one optional wiring pattern and an interconnect option to the at least one optional wiring pattern.Type: ApplicationFiled: January 26, 2005Publication date: June 16, 2005Inventors: Hsiao-Hui Chen, Cheng-Hsiung Kuo
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Patent number: 6906958Abstract: A programmable memory circuit includes a memory array having a plurality of floating gate memory cells disposed in a first and second row and at least a first and second column and a reference circuit for providing a word line voltage to the memory array for programming selected memory cells from a selected one of the first and second rows. The word line voltage is dependent at least in part upon a bit line reference voltage and upon a threshold voltage of a reference floating gate cell associated with the selected one of the first and second rows.Type: GrantFiled: March 26, 2003Date of Patent: June 14, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yue-Der Chih, Cheng-Hsiung Kuo