Abstract: An optical imaging lens including a first lens, a second lens, an aperture, a third lens and a fourth lens arranged in sequence from an object side to an image side along an optical axis. The optical imaging lens includes, from an object side to an image side, the first lens having negative refractive power and including an image-side surface being concave, the second lens having positive refractive power and including an image-side surface being convex, the third lens having refractive power and including an object-side surface being convex and the fourth lens having refractive power. The optical imaging lens includes a total of four lenses.

Abstract: A semiconductor device including an integrated circuit, a dielectric layer, a plurality of connecting terminals and at least one dummy conductor is provided. The integrated circuit has a plurality of connecting pads, and the dielectric layer is disposed thereon and partially exposes the plurality of the connecting pads by a plurality of openings defined therein. The plurality of the connecting terminals is disposed on the plurality of the connecting pads exposed by the plurality of the openings. The at least one dummy conductor is disposed on the dielectric layer and electrically isolated from the integrated circuit. A substantial topology variation is between the plurality of the connecting terminals and the at least one dummy conductor. A semiconductor package having the semiconductor device is also provided.

Abstract: In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a first semiconductor layer including a stand-off feature. A bond pad layer is formed over the first semiconductor layer and the stand-off feature. The bond pad layer is patterned to form a first bond pad over the stand-off feature and a second pad over a portion of the first semiconductor layer. An annealing process is performed to increase a surface roughness of the first bond pad and the second pad. The first semiconductor layer is patterned to form a micro-electromechanical systems (MEMS) structure including a movable element. A device die is bonded to the stand-off feature. The second pad is over the movable element.

Abstract: Some embodiments relate to an integrated device, including a substrate having a first side and a second side opposite the first side, the substrate being a first material; a first wire level on the first side of the substrate and having a first wire; a second wire level on the second side of the substrate and having a second wire; a through-substrate via (TSV) extending from the first wire to the second wire through the substrate; a shallow trench isolation (STI) region surrounding the TSV at the second side of the substrate; and a semiconductor region between the STI region and the TSV, the semiconductor region comprising the first material.

Abstract: A pellicle including a pellicle membrane with improved stability to hydrogen plasma is provided. The pellicle membrane includes a plurality of carbon nanotubes (CNTs), where at least one carbon nanotube (CNT) of the plurality of CNTs is coated by a protection coating. The protection coating includes a plurality of nanostructures that includes a transition metal or an oxide, nitride, silicide or carbide thereof on a surface of the at least one CNT of the plurality of CNTs, a carbon-based diffusion barrier layer over at least the plurality of nanostructures, and a capping layer over at least the carbon-based diffusion barrier layer. The pellicle further includes a pellicle border attached to the pellicle membrane along a peripheral region of the pellicle membrane and a pellicle frame attached to the pellicle border.

Abstract: An EUV lithography mask including a substrate, a patterned absorber layer including an alloy of rhodium. In some embodiments, the alloy of rhodium includes a group 5, group 6, group 9, group 10, or group 11 transition metal having a specific EUV refractive index and a specific EUV extinction coefficient. The disclosed EUV lithography masks reduce undesirable mask 3D effects.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed over the substrate, a capping layer disposed over the reflective multilayer, an intermediate layer disposed over the capping layer, an absorber layer disposed over the intermediate layer, and a cover layer disposed over the absorber layer. The intermediate layer includes a material having a lower hydrogen diffusivity than a material of the capping layer.

Abstract: Coated nanotubes and bundles of nanotubes are formed into membranes useful in optical assemblies in EUV photolithography systems. These optical assemblies are useful in methods for patterning materials on a semiconductor substrate. Such methods involve generating, in a UV lithography system, UV radiation. The UV radiation is passed through a coating layer of the optical assembly, e.g., a pellicle assembly. The UV radiation that has passed through the coating layer is passed through a matrix of individual nanotubes or matrix of nanotube bundles. UV radiation that passes through the matrix of individual nanotubes or matrix of nanotube bundles is reflected from a mask and received at a semiconductor substrate.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes one or more alternating pairs of a first Cr based layer and a second Cr based layer different from the first Cr based layer.

Abstract: An electronic device includes a plurality of treatment components. The treatment components include a first treatment component and a second treatment component, wherein the first treatment component and the second treatment component are independently controlled. Therefore, the convenience of use may be increased, or the treatment effect on the target area may be increased.

Abstract: Coated nanotubes and bundles of nanotubes are formed into membranes useful in optical assemblies in EUV photolithography systems. These optical assemblies are useful in methods for patterning materials on a semiconductor substrate. Such methods involve generating, in a UV lithography system, UV radiation. The UV radiation is passed through a coating layer of the optical assembly, e.g., a pellicle assembly. The UV radiation that has passed through the coating layer is passed through a matrix of individual nanotubes or matrix of nanotube bundles. UV radiation that passes through the matrix of individual nanotubes or matrix of nanotube bundles is reflected from a mask and received at a semiconductor substrate.

Abstract: A method for forming a pellicle for an extreme ultraviolet lithography is provided. The method includes forming a pellicle membrane over a filter membrane and transferring the pellicle membrane from the filter membrane to a membrane border. Forming the pellicle membrane includes growing carbon nanotubes (CNTs) from in-situ formed metal catalyst particles in a first reaction zone of a reactor, each of the CNTs including a metal catalyst particle at a growing tip thereof, growing boron nitride nanotubes (BNNTs) to surround individual CNTs in a second reaction zone of the reactor downstream of the first reaction zone, thereby forming heterostructure nanotubes each including a CNT core and a BNNT shell, and collecting the heterostructure nanotubes on the filter membrane. The metal catalyst particles are partially or completely removed during growing the BNNTs.

Abstract: A stereoscopic image generating method is provided. The method includes: processing a first image to obtain depth data of each pixel in the first image, and generating a first depth-information map, wherein the first depth-information map includes depth information corresponding to each pixel; performing uniform processing on a plurality of edge pixels which are within a predetermined width from a plurality of edges of the first depth-information map, so that the processed edge pixels have the same depth information to establish a second depth-information map; setting a pixel offset corresponding to each pixel in the first image based on the depth information corresponding to each pixel of the second depth-information map; performing pixel offset processing on the first image to generate a second image; and outputting the first image and the second image to the display unit to display a stereoscopic image.

Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.

Abstract: A reticle carrier includes an inner pod, a first auxiliary structure, and an outer pod. The inner pod is configured to receive a reticle. The inner pod comprises an inner baseplate and an inner cover plate, and an inner surface of the inner baseplate and an inner surface of the inner cover plate face each other. The first auxiliary structure is on one of the inner surface of the inner baseplate and the inner surface of the inner cover plate. The first auxiliary structure includes a raised structure and a contact pattern on the raised structure, and the contact pattern includes a plurality of parallel strips. The outer pod houses the inner pod.

Abstract: A planar insulating spacer layer can be formed over a substrate, and a combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode can be formed over the planar insulating spacer layer. A dielectric matrix layer is formed thereabove. A source-side via cavity and a drain-side via cavity can be formed through the dielectric matrix layer over end portions of the semiconducting material layer. Mechanical stress can be generated between the end portions of the semiconducting material layer by changing a lattice constant of end portions of the semiconducting material layer. The mechanical stress can enhance the mobility of charge carriers in a channel portion of the semiconducting material layer.

Abstract: A downlink bandwidth control method is applicable to a network device including a first queue for first traffic and a second queue for second traffic, and includes: determining whether traffic the network device is receiving meets a predetermined criterion associated with the first traffic; acquiring a total downlink bandwidth between the network device and another network device; and in response to determining that the traffic the network device is receiving meets the predetermined criterion associated with the first traffic, setting an upper bound of a download speed of the second traffic to a decreased value according to the total downlink bandwidth, wherein the decreased value is equal to a portion of the total downlink bandwidth.

Abstract: In a method of cleaning a photo mask, the photo mask is placed on a support such that a pattered surface faces down, and an adhesive sheet is applied to edges of a backside surface of the photo mask.

Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.

Abstract: A level shifter with high reliability is shown, which has a power multiplexer receiving a plurality of power voltage candidates to selectively output a selected power voltage. In response to a low-to-high transition of the input signal of the level shifter, the first output terminal of the level shifter is pulled up to the selected power voltage by the second pull-up device, and the first pull-down device pulls down the second output terminal of the level shifter to a low-voltage level corresponding to the selected power voltage. In response to a high-to-low transition of the input signal, the second output terminal of the level shifter is pulled up to the selected power voltage by the first pull-up device, and the second pull-down device pulls down the first output terminal of the level shifter to the low-voltage level corresponding to the selected power voltage.