Abstract: Various embodiments of the present disclosure are directed towards an image sensor including first chip and a second chip. The first chip includes a first substrate, a plurality of photodetectors disposed in the first substrate, a first interconnect structure disposed on a front side of the first substrate, and a first bond structure disposed on the first interconnect structure. The second chip underlies the first chip. The second chip includes a second substrate, a plurality of semiconductor devices disposed on the second substrate, a second interconnect structure disposed on a front side of the second substrate, and a second bond structure disposed on the second interconnect structure. A first bonding interface is disposed between the second bond structure and the first bond structure. The second interconnect structure is electrically coupled to the first interconnect structure by way of the first and second bond structures.

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

Abstract: A semiconductor device includes a first contact layer, a second contact layer, an active layer, a photonic crystal layer, a passivation layer, a first electrode and a second electrode. The first contact layer has a first surface and a second surface opposite to each other. Microstructures are located on the second surface. The second contact layer is located below the first surface. The active layer is located between the first contact layer and the second contact layer. The photonic crystal layer is located between the active layer and the second contact layer. The passivation layer is located on the second contact layer. The first electrode is located on the passivation layer and is electrically connected the first surface of the first contact layer. The second electrode is located on the passivation layer and is electrically connected to the second contact layer.

Abstract: A method includes forming a test pattern and a reference pattern in an absorption layer of a photomask structure. The test pattern has a first trench and a second trench, the reference pattern has a third trench and a fourth trench, the test pattern and the reference pattern have substantially the same dimension in a top view, and the second trench is deeper than the first trench, the third trench, and the fourth trench. The method further includes emitting a light beam to the test pattern to obtain a first interference pattern reflected from the test pattern, emitting the light beam to the reference pattern to obtain a second interference pattern reflected from the reference pattern; and comparing the first interference pattern with the second interference pattern to obtain a measured complex refractive index of the absorption layer.

Abstract: A method of making a sealing article that includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.

Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing a semiconductor structure. The semiconductor structure includes a substrate, semiconductor structures, an isolation layer, an adhesive layer, a metal layer, a metal nitride layer, a semiconductor layer, a profile modifier layer, and a disconnection structure. The semiconductor structures are disposed on the substrate. The isolation layer is disposed between the semiconductor structures. The metal layer is disposed on an adhesive layer. The metal nitride layer is disposed on the metal layer. The semiconductor layer is disposed on the metal nitride layer. The profile modifier layer is disposed on the semiconductor layer. The disconnection structure is disposed and extending from the profile modifier layer to the isolation layer. A first width of the disconnection structure in the profile modifier layer is substantially the same as a second width of the disconnection structure in the isolation layer.

Abstract: An electronic device includes a light emitting layer, a light conversion layer and an adjustable structure. The light emitting layer has a plurality of light emitting units for emitting light. The light conversion layer converts the wavelength of the light emitted by at least one light emitting unit to provide converted light. The adjustable structure is controlled to adjust a light penetrating area to correspond to the affected part to be treated, wherein at least one of the light and the converted light passes through the light penetrating area to irradiate the affected part.

Abstract: In a method of manufacturing a pellicle for an extreme ultraviolet (EUV) photomask, a nanotube layer including a plurality of carbon nanotubes is formed, the nanotube layer is attached to a pellicle frame, and a solvent dipping treatment is performed to the nanotube layer by applying bubbles in a solvent to the nanotube layer.

Abstract: A method for forming a package structure is provided, including forming an interconnect structure over a carrier substrate and forming a semiconductor die over a first side of the interconnect structure. A removable film is formed over the semiconductor die. The method includes forming a first stacked die package structure over the first side of the interconnect structure. A top surface of the removable film is higher than a top surface of the first stacked die package structure. The method includes forming a package layer, removing a portion of the package layer to expose a portion of the removable film, removing the removable film to form a recess, forming a lid structure over the semiconductor die and the first stacked die package structure. The lid structure has a main portion and a protruding portion disposed in the recess and extending from the main portion.

Abstract: The application relates to a light-emitting assembly including a substrate and an effective light-emitting region. The substrate has a first surface and a second surface that are opposite to each other and has a transparent material. The light shielding layer is disposed on the first surface of the substrate, and a first edge and a second edge of the light shielding layer are spaced apart from each other, thereby forming an opening. The effective light-emitting region is defined on the second surface of the substrate, and the effective light-emitting region and the first edge of the light shielding layer are offset by a first distance in a lateral direction. The first distance is associated with a refractive index of the substrate, a refractive index of a material in the opening of the light shielding layer, and a thickness of the substrate.

Abstract: A reflective mask includes a reflective multilayer over a substrate, a capping layer over the reflective multilayer, an absorber layer over the capping layer and including a top surface, and a protection layer directly on the top surface of the absorber layer. The absorber layer is formed of a first material and the protection layer is formed of a second material that is less easily to be oxidized than the first material.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor layer, a micro-electromechanical systems (MEMS) structure defined in the semiconductor layer, a bond ring over the semiconductor layer, and a cap structure over the MEMS structure and bonded to the bond ring. The MEMS structure has an upper surface and the cap structure has a lower surface facing the upper surface of the MEMS structure. Dimples of eutectic material are on the upper surface of the MEMS structure.

Abstract: A method includes performing a lithography process using a mask and a pellicle membrane; detaching the pellicle membrane from the mask after the lithography process is completed; performing an inspection process to the pellicle membrane, the inspection process including generating a laser beam toward the pellicle membrane from a laser source, such that the laser beam passes through the pellicle membrane; and generating an image by receiving the laser beam passing through the pellicle membrane using an image sensor; and determining whether a particle is present on the pellicle membrane or a pin hole is present in the pellicle membrane based on the image.

Abstract: A level shifter and a chip with the level shifter are shown. Between the input pair and the cross-coupled output pair, there are a first protection circuit and a second protection circuit. An overdrive voltage, which is double the nominal voltage of the level shifter plus a delta voltage, is applied to the level shifter. The first protection circuit has a first voltage-drop circuit that compensates for the delta voltage. The second protection circuit has a second voltage-drop circuit that compensates for the delta voltage.

Abstract: A downlink bandwidth control method is applicable to a network device including a first queue for first traffic and a second queue for second traffic, and includes: determining whether traffic the network device is receiving meets a predetermined criterion associated with the first traffic; acquiring a total downlink bandwidth between the network device and another network device; and in response to determining that the traffic the network device is receiving meets the predetermined criterion associated with the first traffic, setting an upper bound of a download speed of the second traffic to a decreased value according to the total downlink bandwidth, wherein the decreased value is equal to a portion of the total downlink bandwidth.

Abstract: A method includes forming a reflective multilayer over a substrate; depositing a first capping layer over the reflective multilayer, wherein the first capping layer is made of a ruthenium-containing material or a chromium-containing material; performing a treatment to the first capping layer to introduce nitrogen or fluorine into the first capping layer; forming an absorption layer over the first capping layer; and patterning the absorption layer.

Abstract: An extreme ultraviolet (EUV) mask includes a substrate, a reflective multilayer stack on the substrate, a diffusion barrier layer, a capping layer and a patterned absorber layer. The reflective multilayer stack comprises alternately stacked first layers and second layers. The diffusion barrier layer is on the reflective multilayer stack. The diffusion barrier layer has a composition different from compositions of the first layers and the second layers. The capping layer is on the diffusion barrier layer. The patterned absorber layer is on the reflective multilayer stack.

Abstract: A 3D format image detection method and an electronic apparatus using the same are provided. The 3D format image detection method includes the following steps. A first image and a second image are obtained by splitting an input image according to a 3D image format. A 3D matching processing is performed on the first image and the second image to generate a disparity map of the first image and the second image. The matching number of a plurality of first pixels in the first image matched with a plurality of second pixels in the second image is calculated according to the disparity map. Whether the input image is a 3D format image conforming to the 3D image format is determined according to the matching number.

Abstract: In a method of manufacturing a pellicle for an extreme ultraviolet (EUV) photomask, a nanotube layer including a plurality of carbon nanotubes is formed, the nanotube layer is attached to a pellicle frame, and a Joule hearting treatment is performed to the nanotube layer by applying electric current through the nanotube layer.

Abstract: In a method of manufacturing a pellicle for an extreme ultraviolet (EUV) photomask, a membrane of Sp2 carbon is formed, a treatment is performed on the membrane to change a surface property of the membrane, and after the treatment, a cover layer is formed over the membrane.