Patents by Inventor Cheng Hsu

Cheng Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING
    Publication number: 20240051818
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor layer, a micro-electromechanical systems (MEMS) structure defined in the semiconductor layer, a bond ring over the semiconductor layer, and a cap structure over the MEMS structure and bonded to the bond ring. The MEMS structure has an upper surface and the cap structure has a lower surface facing the upper surface of the MEMS structure. Dimples of eutectic material are on the upper surface of the MEMS structure.
    Type: Application
    Filed: August 9, 2022
    Publication date: February 15, 2024
    Inventors: Hsi-Cheng HSU, Chen-Wei CHIANG, Jui-Chun WENG, Hsin-Yu CHEN, Chia Yu LIN
  • INSPECTION METHOD FOR PELLICLE MEMBRANE OF LITHOGRAPHY SYSTEM
    Publication number: 20240053676
    Abstract: A method includes performing a lithography process using a mask and a pellicle membrane; detaching the pellicle membrane from the mask after the lithography process is completed; performing an inspection process to the pellicle membrane, the inspection process including generating a laser beam toward the pellicle membrane from a laser source, such that the laser beam passes through the pellicle membrane; and generating an image by receiving the laser beam passing through the pellicle membrane using an image sensor; and determining whether a particle is present on the pellicle membrane or a pin hole is present in the pellicle membrane based on the image.
    Type: Application
    Filed: August 11, 2022
    Publication date: February 15, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia Hao CHANG, Pei-Cheng HSU, Chih-Cheng CHEN, Huan-Ling LEE, Ting-Hao HSU, Hsin-Chang LEE
  • Level shifter and chip with overdrive capability
    Patent number: 11901892
    Abstract: A level shifter and a chip with the level shifter are shown. Between the input pair and the cross-coupled output pair, there are a first protection circuit and a second protection circuit. An overdrive voltage, which is double the nominal voltage of the level shifter plus a delta voltage, is applied to the level shifter. The first protection circuit has a first voltage-drop circuit that compensates for the delta voltage. The second protection circuit has a second voltage-drop circuit that compensates for the delta voltage.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: February 13, 2024
    Assignee: MEDIATEK INC.
    Inventors: Federico Agustin Altolaguirre, Hsin-Cheng Hsu
  • METHOD FOR CONTROLLING DOWNLOAD SPEED OF NORMAL TRAFFIC IN THE PRESENCE OF HIGH-PRIORITY TRAFFIC AND ASSOCIATED NETWORK DEVICE
    Publication number: 20240048507
    Abstract: A downlink bandwidth control method is applicable to a network device including a first queue for first traffic and a second queue for second traffic, and includes: determining whether traffic the network device is receiving meets a predetermined criterion associated with the first traffic; acquiring a total downlink bandwidth between the network device and another network device; and in response to determining that the traffic the network device is receiving meets the predetermined criterion associated with the first traffic, setting an upper bound of a download speed of the second traffic to a decreased value according to the total downlink bandwidth, wherein the decreased value is equal to a portion of the total downlink bandwidth.
    Type: Application
    Filed: August 8, 2022
    Publication date: February 8, 2024
    Applicant: MEDIATEK INC.
    Inventors: I-Hei Ng, Wei-Lun Liu, Kun-Cheng Hsu
  • MASK AND METHOD FOR FORMING THE SAME
    Publication number: 20240045317
    Abstract: A method includes forming a reflective multilayer over a substrate; depositing a first capping layer over the reflective multilayer, wherein the first capping layer is made of a ruthenium-containing material or a chromium-containing material; performing a treatment to the first capping layer to introduce nitrogen or fluorine into the first capping layer; forming an absorption layer over the first capping layer; and patterning the absorption layer.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 8, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chang LEE, Ping-Hsun LIN, Pei-Cheng HSU, Hsuan-I WANG, Hung-Yi TSAI, Bo-Wei SHIH, Ta-Cheng LIEN
  • EXTREME ULTRAVIOLET MASK WITH DIFFUSION BARRIER LAYER
    Publication number: 20240045318
    Abstract: An extreme ultraviolet (EUV) mask includes a substrate, a reflective multilayer stack on the substrate, a diffusion barrier layer, a capping layer and a patterned absorber layer. The reflective multilayer stack comprises alternately stacked first layers and second layers. The diffusion barrier layer is on the reflective multilayer stack. The diffusion barrier layer has a composition different from compositions of the first layers and the second layers. The capping layer is on the diffusion barrier layer. The patterned absorber layer is on the reflective multilayer stack.
    Type: Application
    Filed: August 3, 2022
    Publication date: February 8, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chang LEE, Pei-Cheng HSU, Wei-Hao LEE, Bo-Wei SHIH, Ta-Cheng LIEN
  • 3D FORMAT IMAGE DETECTION METHOD AND ELECTRONIC APPARATUS USING THE SAME METHOD
    Publication number: 20240046608
    Abstract: A 3D format image detection method and an electronic apparatus using the same are provided. The 3D format image detection method includes the following steps. A first image and a second image are obtained by splitting an input image according to a 3D image format. A 3D matching processing is performed on the first image and the second image to generate a disparity map of the first image and the second image. The matching number of a plurality of first pixels in the first image matched with a plurality of second pixels in the second image is calculated according to the disparity map. Whether the input image is a 3D format image conforming to the 3D image format is determined according to the matching number.
    Type: Application
    Filed: December 2, 2022
    Publication date: February 8, 2024
    Applicant: Acer Incorporated
    Inventors: Kai-Hsiang Lin, Hung-Chun Chou, Wen-Cheng Hsu, Shih-Hao Lin, Chih-Haw Tan
  • PELLICLE FOR EUV LITHOGRAPHY MASKS AND METHODS OF MANUFACTURING THEREOF
    Publication number: 20240036462
    Abstract: In a method of manufacturing a pellicle for an extreme ultraviolet (EUV) photomask, a nanotube layer including a plurality of carbon nanotubes is formed, the nanotube layer is attached to a pellicle frame, and a Joule hearting treatment is performed to the nanotube layer by applying electric current through the nanotube layer.
    Type: Application
    Filed: February 24, 2023
    Publication date: February 1, 2024
    Inventors: Pei-Cheng HSU, Ting-Pi Sun, Hsin-Chang Lee
  • PELLICLE FOR EUV LITHOGRAPHY MASKS AND METHODS OF MANUFACTURING THEREOF
    Publication number: 20240036459
    Abstract: In a method of manufacturing a pellicle for an extreme ultraviolet (EUV) photomask, a membrane of Sp2 carbon is formed, a treatment is performed on the membrane to change a surface property of the membrane, and after the treatment, a cover layer is formed over the membrane.
    Type: Application
    Filed: March 23, 2023
    Publication date: February 1, 2024
    Inventors: Wei-Hao LEE, Pei-Cheng HSU, Chia-Tung KUO, Hsin-Chang LEE
  • Semiconductor device encapsulated by molding material attached to redistribution layer
    Patent number: 11887952
    Abstract: A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: January 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Puu Jeng, Shuo-Mao Chen, Feng-Cheng Hsu
  • Driving circuit of active-matrix organic light-emitting diode with hybrid transistors
    Patent number: 11887537
    Abstract: A driving circuit includes a first transistor, a second transistor and a third transistor. The first transistor has a first terminal connected to a first voltage level, a second terminal, and a third terminal. The second transistor has a first terminal connected to the second terminal of the first transistor, a second terminal connected to a second voltage level, and a third terminal connected to the third terminal of the first transistor. The third transistor has a first terminal connected to the first terminal of the second transistor. The first transistor and the second transistor are low temperature poly-silicon transistors, and the third transistor is an oxide semiconductor transistor.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: January 30, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Lien-Hsiang Chen, Kung-Chen Kuo, Ming-Chun Tseng, Cheng-Hsu Chou, Kuan-Feng Lee
  • LIGHT-EMITTING ELEMENT
    Publication number: 20240032330
    Abstract: A light-emitting element comprises a substrate, a light shielding layer, a capping layer and a plurality of protrusions. The light shielding layer is above the substrate. The capping layer is above the light shielding layers. The plurality of protrusions is arranged over the substrate, an organic light-emitting unit comprising an organic material being disposed between two adjacent protrusions of the plurality of protrusions. An edge of the light shielding layer is misaligned with an edge of one of the plurality of protrusions. The organic light-emitting unit includes a first light-emitting unit and a second light-emitting unit. The first light-emitting unit and the second light-emitting unit respectively have an organic light-emitting stack layer comprising an organic material.
    Type: Application
    Filed: May 15, 2023
    Publication date: January 25, 2024
    Inventors: HUEI-SIOU CHEN, LI-CHEN WEI, KUO-CHENG HSU
  • LIGHT EMITTING DEVICE AND KEYBOARD STRUCTURE
    Publication number: 20240028134
    Abstract: A light emitting device and a keyboard structure are provided. The light emitting device includes a circuit board and multiple light emitting units. The circuit board includes a substrate, a first conductive pad, multiple second conductive pads, and multiple third conductive pads. The first conductive pad and the second conductive pads are disposed on a first board surface of the substrate. The first conductive pad has a symmetrical shape and a symmetrical axis. The symmetrical axis passes through the second conductive pads. The third conductive pads are disposed on a second board surface of the substrate. Each of the third conductive pads is electrically coupled to the first conductive pad and the second conductive pads by multiple conductive columns. Each of the light emitting units is connected to the first conductive pad and one of the second conductive pads.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 25, 2024
    Inventors: SHAN-HUI CHEN, PO-JUI LIN, CHANG-HUNG HSIEH, PO-CHENG HSU
  • Post driver and chip with overdrive capability
    Patent number: 11881847
    Abstract: A post driver and a chip with overdrive capability are shown. A first bias circuit is configured to provide a first voltage shift between the output terminal of the post driver and the gate terminal of the first p-channel metal-oxide-semiconductor (PMOS) transistor of a pull-up circuit when the pull-down circuit is enabled. A second bias circuit is configured to provide a second voltage shift between the output terminal of the post driver and the gate terminal of the first n-channel metal-oxide-semiconductor (NMOS) transistor of the pull-down circuit when the pull-up circuit is enabled. Accordingly, the PMOS transistors in the pull-up circuit and the NMOS transistors in the pull-down circuit are all well protected although they are powered by an overdrive voltage.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: January 23, 2024
    Assignee: MEDIATEK INC.
    Inventors: Federico Agustin Altolaguirre, Hsin-Cheng Hsu
  • LIGHT-EMITTING ELEMENT
    Publication number: 20240023386
    Abstract: A light-emitting element comprises a substrate, a plurality of light shielding layers, a capping layer, a conductive layer and a plurality of protrusions. The plurality of light shielding layers is under the substrate. The capping layer contacts a first surface of the substrate and covers the plurality of light shielding layers. The conductive layer contacts a second surface of the substrate. The plurality of protrusions is arranged on the second surface of the substrate and covers a part of the conductive layer, and an organic light-emitting unit comprising an organic material is disposed between two adjacent protrusions of the plurality of protrusions. One of the plurality of protrusions has an edge, which is offset from an edge of one of the plurality of light shielding layers in the longitudinal direction from each other.
    Type: Application
    Filed: May 15, 2023
    Publication date: January 18, 2024
    Inventors: HUEI-SIOU CHEN, KUO-CHENG HSU, LI-CHEN WEI
  • Method for Three Dimensional Medical Image Construction
    Publication number: 20240013473
    Abstract: A method for three dimensional medical image construction having steps of inputting multiple two-dimensional images and a known three-dimensional image into a processing module and inputting a new two-dimensional image into the processing module to obtain a reconstructed three-dimensional image, wherein the processing module utilizes a neural network to build a reconstructed three-dimensional image by unfolding the two-dimensional image to produce a three-dimensional reconstruction.
    Type: Application
    Filed: June 16, 2023
    Publication date: January 11, 2024
    Inventors: Yi-Wen Chen, Cheng-Ting Shih, Kui-Chou Huang, Hsin-Yuan Fang, Kai-Cheng Hsu
  • ESTABLISHING METHOD OF SLEEP APNEA ASSESSMENT PROGRAM, SLEEP APNEA ASSESSMENT SYSTEM, AND SLEEP APNEA ASSESSMENT METHOD
    Publication number: 20240008765
    Abstract: A sleep apnea assessment method includes the following steps. A sleep apnea assessment system is provided. A target ECG signal data of the subject is obtained. A data pre-processing step is performed so as to obtain a target ECG time-frequency data, and the target ECG time-frequency data is processed so as to obtain a plurality of target time-frequency segment data. An assessing step of apnea event is performed so as to output an assessing result of sleep apnea event of each of the plurality of target time-frequency segment data, and the assessing result of sleep apnea event is for assessing whether the subject has the sleep apnea event in any one of the plurality of target time-frequency segment data or not and predicting a probability of an occurrence of sleep apnea event of the subject.
    Type: Application
    Filed: January 10, 2023
    Publication date: January 11, 2024
    Applicant: China Medical University
    Inventors: Kai-Cheng Hsu, Liang-Wen Hang, Ya-Lun Wu, Meng-Hsuan Liu
  • SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20240014180
    Abstract: A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.
    Type: Application
    Filed: September 21, 2023
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Kuei Hsu, Feng-Cheng Hsu, Ming-Chih Yew, Po-Yao Lin, Shuo-Mao Chen, Shin-Puu Jeng
  • Pellicle and method of using the same
    Patent number: 11868041
    Abstract: A pellicle frame includes a check valve, wherein the check valve is configured to permit gas flow from an interior of the pellicle to an exterior of the pellicle. The pellicle frame further includes a bottom surface of the frame defines only a single recess therein. The pellicle frame further includes a gasket configured to fit within the single recess.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: January 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chue San Yoo, Hsin-Chang Lee, Pei-Cheng Hsu, Yun-Yue Lin
  • CHIP PACKAGE STRUCTURE HAVING MOLDING LAYER
    Publication number: 20240006367
    Abstract: A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive pillar over the first surface and adjacent to the first chip. The chip package structure includes a second chip over the second surface. The chip package structure includes a second conductive pillar over the second surface and adjacent to the second chip. The chip package structure includes a first molding layer over the first surface and surrounding the first chip. The chip package structure includes a second molding layer over the second surface and surrounding the second chip.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 4, 2024
    Inventors: Shin-Puu JENG, Shuo-Mao CHEN, Feng-Cheng HSU