Abstract: A circuit board structure includes a core, a wiring layer and a buried passive component. The wiring layer and the buried passive component are disposed on the core, and the buried passive component is electrically connected to the wiring layer. The buried passive component includes a first spiral metal layer, a second spiral metal layer and a dielectric interlayer. The first spiral metal layer is intertwined with the second spiral metal layer. The dielectric interlayer is disposed between the first spiral metal layer and the second spiral metal layer. The first spiral metal layer and the second spiral metal layer are spaced apart by the dielectric interlayer at least in the core.

Abstract: A tongue plate includes a number of first conductive pads and a conductive shielding assembly. The conductive pads include a first signal terminal group, a first ground terminal and a second ground terminal. The conductive shielding assembly includes a first conductive shielding plate in contact with the first ground terminal, a second conductive shielding plate in contact with the second ground terminal, and a connecting plate connecting the first conductive shielding plate and the second conductive shielding plate. The first conductive shielding plate, the second conductive shielding plate and the connecting plate jointly form a first conductive shielding cavity. The first signal terminal group is located at a first opening of the first conductive shielding chamber. Such arrangement improves the signal shielding effect of the tongue plate and reduces signal crosstalk.

Abstract: A method of forming a semiconductor device includes: forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, where the opening exposes an upper surface of the via; selectively forming a capping layer over the upper surface of the via, where the capping layer has a curved upper surface that extends above a first upper surface of the first dielectric layer distal from the substrate; after forming the capping layer, forming a barrier layer in the opening over the capping layer and along sidewalls of the second dielectric layer exposed by the opening; and filling the opening by forming an electrically conductive material over the barrier layer.

Abstract: A ferroelectric random access memory (FeRAM) cell may include an oxide insertion layer between the electron barrier layer and the metal glue layer of the source/drain regions of the FeRAM cell. The oxide insertion layer may improve the thermal stability of the electron barrier layer and minimize or prevent dissociation and/or out-diffusion of the electron barrier layer at high processing temperatures. Thus, the oxide insertion layer may enable the metal glue layer to be formed over the electron barrier layer with low surface roughness, which may enable increased adhesion between the metal glue layer and the source/drain electrodes of the source/drain regions. In this way, the oxide insertion layer may enable low electrical resistance to be achieved for the FeRAM cell and/or may reduce the likelihood of failures in the FeRAM cell, among other examples.

Abstract: Embodiments receive a plurality of incoming requests, determine that the plurality of incoming requests comprise a plurality of instant requests, create a software image based on the instant requests, and pull the software image based on a deployed configuration.

Abstract: Disclosed are a reverse soldering connection structure of a microneedle and a wiring and a preparation process thereof. The reverse soldering metal layer of the microneedle is prepared; the reverse soldering metal layer of the wiring is prepared; the reverse soldering metal layer of the microneedle is aligned with the reverse soldering metal layer of the wiring, and they will be pressed to achieve reverse soldering connection between the microneedle and the wiring.

Abstract: Various embodiments herein relate to methods and apparatus for etching a feature in a substrate. Often, the feature is etched in the context of forming a DRAM or other memory device. The feature is etched in dielectric material, which often includes a silicon oxide. The feature is etched using chemistry that includes a metal-containing gas such as tungsten hexafluoride. Although other metal-containing gases are commonly used as deposition gases (e.g., to deposit metal-containing films), they can also be used during etching. Advantageously, the inclusion of a metal-containing gas in the etch chemistry can increase the selectivity of the etch and/or improve the feature-to-feature uniformity (e.g., improve LCDU).

Abstract: A backlight module includes a light guide plate, a light source, and an optical film. The light guide plate has a light incident surface and a light exiting surface opposite to the light incident surface, in which the light exiting surface has a normal line. The light source is adjacent to the light incident surface. The optical film is disposed to the light exiting surface and includes plural parallel prisms and plural microstructures. An extending direction of each of the prisms is perpendicular to the normal line, and each of the prisms faces the light exiting surface of the light guide plate. Each of the microstructures is located on a surface of the optical film which faces away from the light guide plate. Each of the microstructures has a pyramid structure with plural facets. The prisms are located between the microstructures and the light exiting surface.

Abstract: A method includes: inspecting a reticle in a reticle pod, the reticle pod including a sealed space to accommodate the reticle, and the reticle pod further comprising a window arranged on an upper surface of the reticle pod, wherein the inspecting is performed through the window; and moving the reticle out of the reticle pod for performing a lithography operation using the reticle.

Abstract: A lithium battery cell includes an upper cover module, a first battery electrode group, a second battery electrode group, and a plurality of first electrode connection straps. The first electrode connection straps are stacked together and have the same width and length. A first end of the first electrode connection straps is welded to a first tab, a second end of the first electrode connection straps is welded to a second tab, and a middle part of the first electrode connection straps is welded to a first electrode terminal. An even number of first bending parts are formed between the middle part and the first end, and an even number of second bending parts are formed between the middle part and the second end, and the first bending parts and the second bending parts are symmetrical to each other. Furthermore, a lithium battery cell manufacturing method is also disclosed therein.

Abstract: A conversion control circuit controls a power stage circuit of a switching power converter according to a first feedback signal and a second feedback signal, wherein the conversion control circuit includes an error amplifier circuit, a ramp signal generation circuit, a pulse width modulation circuit, and a quick response control circuit. The quick response control circuit performs a quick response control function, wherein the quick response control function includes: comparing the second feedback signal with at least one reference threshold to generate a quick response control signal; and when the second feedback signal crosses the reference threshold, adjusting a slope of a ramp signal according to the quick response control signal to accelerate an increase or decrease of the duty of a PWM signal, thereby accelerating the transient response of the switching power converter.

Abstract: A memory socket includes a frame having a base portion and a side portion, and a push-eject locking mechanism in physical communication with the base portion and with the side portion. The push-eject locking mechanism to transition between an unlocked position and a locked position. The push-eject locking mechanism includes an eject bar component and a lever component. The weight of the eject bar component biases the push-eject locking mechanism towards the unlocked position. Based on a force being exerted on the lever component, the lever component pivots and transition the push-eject locking mechanism from the unlocked position to the locked position.

Abstract: A photonic integrated circuit structure includes a semiconductor substrate. A waveguide is disposed above the semiconductor substrate and has an inclined plane. A mirror coating layer is conformally disposed on the inclined plane. A cladding layer covers the waveguide and the mirror coating layer. A hole is disposed in the semiconductor substrate or the cladding layer, and the hole overlaps the inclined plane in a vertical direction. In addition, an optical fiber is disposed in the hole to receive a reflected light from the mirror coating layer.

Abstract: The present disclosure provides the use of an anti-PD-1 antibody in combination with famitinib in the preparation of a drug for treating tumors. In the present technical solution, toxicity is controllable and tolerable. At the same time, the described drug combination effectively reduces adverse reactions to the anti-PD-1 antibody, such as the occurrence of reactive capillary endothelial proliferation.

Abstract: A video decoder may be configured to receive a block of video data that was encoded using a coding mode that includes a search process in one or more reference frames. The video decoder may prefetch reference samples in a fixed search region of at least one reference frame of the one or more reference frames, and decode the block of video data using the coding mode, including performing the search process for the coding mode using the prefetched reference samples.

Abstract: A power ground noise reduction system includes a bandgap circuit and a noise reduction circuit. The bandgap circuit includes an input terminal for receiving a working voltage, and an output terminal for outputting a bandgap reference voltage. The noise reduction circuit includes a first input terminal coupled to the output terminal of the bandgap circuit for receiving the bandgap reference voltage, a second input terminal for receiving the working voltage, a ground terminal coupled to a low voltage terminal, a first current source for receiving the working voltage received by the second input terminal and generating a first current, and a second current source for generating a second current to the low voltage terminal through the ground terminal.

Abstract: A liquid crystal display (LCD) of the chiral polymer stabilized alignment (C-PSA) mode, a method of its production and its use as an energy-saving display.

Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.

Abstract: A heat dissipation assembly is disclosed and includes a fan, a vapor chamber and a heat dissipation fin set. The fan includes a fan frame, an impeller and a fan cover. The impeller is disposed on the fan frame and accommodated in an accommodation space. The impeller includes plural metal blades and a hub, and the plural metal blades are radially arranged on the periphery of the hub to form a dense-metal-blade impeller. The fan cover is assembled with the fan frame to form an outlet, and the fan cover includes an inlet. The vapor chamber includes an upper plate and a lower plate assembled with each other. The upper plate or the lower plate is connected to the fan cover, and the vapor chamber and the fan cover are coplanar. The heat dissipation fin set is connected to the lower plate and spatially corresponding to the outlet.

Abstract: A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.