Patents by Inventor Cheng Huang
Cheng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240121899Abstract: An electronic device includes a substrate, a plurality of flexible circuit boards, a plurality of ICs and an insulator. The flexible circuit boards are disposed on the substrate. In a top view of the electronic device, the flexible circuit boards are overlapped with an edge of the substrate. The ICs are disposed on the substrate. The insulator is disposed on the flexible circuit boards and contacted the ICs, wherein the insulator has a first side and a second side opposite to the first side and the first side is closer to the edge than the second side. Along a first direction perpendicular to an extension direction of the edge, a first minimum distance between the second side and one of the ICs is less than a second minimum distance between the second side and one of the flexible circuit boards.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Inventors: Chin-Cheng Kuo, Chia-Chun Yang, Wen-Cheng Huang
-
Publication number: 20240118155Abstract: A heavy-duty, high-power and large-torque chassis dynamometer for a multi-environmental system, comprising a power testing platform disposed on the ground and a rack located below the power testing platform. A fixed base and a sliding base are sequentially disposed on an inner side of the rack in a length direction of the power testing platform, a pair of first hub assemblies are mounted on the fixed base through a plurality of support frames, a sliding platform is disposed on the sliding base, and a pair of second hub assemblies are mounted on the sliding platform through a plurality of support frames. Tension sensor assemblies are connected to outer circumferences of the first hub assemblies and outer circumferences of the second hub assemblies, and are fixedly disposed on the support frames.Type: ApplicationFiled: March 2, 2021Publication date: April 11, 2024Applicant: JiangSu XCMG Construction Machinery Research Institute LTD.Inventors: Bin Zhao, Hanguang LIU, Wei XU, Cheng HUANG, Lei TIAN
-
Publication number: 20240116724Abstract: A container feeding device includes a casing and first and second latch members. The casing defines a lower retaining space for receiving a plurality of containers that are stacked on one another. The first latch member is operable to enter the lower retaining space for supporting a bottommost container, or leave the lower retaining space to release the bottommost container. The second latch member enters the lower retaining space to support a second bottommost container when the bottommost container is released by the first latch member.Type: ApplicationFiled: July 27, 2023Publication date: April 11, 2024Applicant: Jabil Inc.Inventors: Harpuneet Singh, Lei Hu, Ying-Chieh Huang, Wei-Hsiu Hsieh, Xiao-Ting Zheng, Chien-Cheng Chu, Arya Anil
-
Publication number: 20240116148Abstract: A tool set includes a tool holder, a tool and a tool rack. The tool has a groove unit. The tool holder has a latch unit that engages the groove unit. The tool rack includes a rack body and a blocking member. When the tool holder is moved away from the rack body after the tool is moved into the rack body by the tool holder and after the blocking member moves to a blocking position, the tool is blocked by the blocking member so that the latch unit is separated from the groove unit and that the tool holder is separated from the tool.Type: ApplicationFiled: August 28, 2023Publication date: April 11, 2024Applicant: Jabil Inc.Inventors: Harpuneet Singh, Lei Hu, Ying-Chieh Huang, Wei-Hsiu Hsieh, Xiao-Ting Zheng, Chien-Cheng Chu, Tike Hoong Phua, Li Yun Chee
-
Publication number: 20240120402Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.Type: ApplicationFiled: November 19, 2023Publication date: April 11, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jia-Ni YU, Kuo-Cheng CHIANG, Mao-Lin HUANG, Lung-Kun CHU, Chung-Wei HSU, Chun-Fu LU, Chih-Hao WANG, Kuan-Lun CHENG
-
Publication number: 20240115616Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.Type: ApplicationFiled: October 4, 2023Publication date: April 11, 2024Inventors: Po-Cheng Lin, Pi-Chun Huang, Zih-Han Hong, Ming-Hsi Chuang, Yi-Chun Lin, Chia-Hsin Lee, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
-
Patent number: 11955507Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.Type: GrantFiled: September 9, 2021Date of Patent: April 9, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Hsin-Hung Li, Wei-Syun Wang, Chih-Chiang Chen, Yu-Cheng Shih, Cheng-Chan Wang, Chia-Hsin Chung, Ming-Jui Wang, Sheng-Ming Huang
-
Patent number: 11953738Abstract: The present invention discloses a display including a display panel and a light redirecting film disposed on the viewing side of the display panel. The light redirecting film comprises a light redistribution layer, and a light guide layer disposed on the light redistribution layer. The light redistribution layer includes a plurality of strip-shaped micro prisms extending along a first direction and arranged at intervals and a plurality of diffraction gratings arranged at the bottom of the intervals between the adjacent strip-shaped micro prisms, wherein each of the strip-shaped micro prisms has at least one inclined light-guide surface, and the bottom of each interval has at least one set of diffraction gratings, and the light guide layer is in contact with the strip-shaped micro prisms and the diffraction gratings.Type: GrantFiled: March 29, 2022Date of Patent: April 9, 2024Assignee: BenQ Materials CorporationInventors: Cyun-Tai Hong, Yu-Da Chen, Hsu-Cheng Cheng, Meng-Chieh Wu, Chuen-Nan Shen, Kuo-Jung Huang, Wei-Jyun Chen, Yu-Jyuan Dai
-
Patent number: 11955370Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.Type: GrantFiled: September 18, 2020Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Cyuan Lu, Ting-Gang Chen, Sung-En Lin, Chunyao Wang, Yung-Cheng Lu, Chi On Chui, Tai-Chun Huang, Chieh-Ping Wang
-
Patent number: 11953344Abstract: A dust-proof sensing device includes a mechanical body, a feeding path, a first photoelectric sensor disposed above the feeding path, a second photoelectric sensor disposed under the feeding path, and an upper bracket. The mechanical body has a feeding path. The upper bracket is mounted above the feeding path. The upper bracket has an upper fastening portion fastened to the mechanical body, an upper wedging portion fastened at the upper fastening portion, an L-shaped upper light guiding holder fastened at the upper fastening portion, and a first light guider fastened at the upper light guiding holder. The upper fastening portion has a first inclined section. An inner edge of an upper surface of the first inclined section is intersected with a top edge of an inner surface of the upper wedging portion to form a clamping angle.Type: GrantFiled: April 11, 2022Date of Patent: April 9, 2024Assignee: Foxlink Image Technology Co., Ltd.Inventors: You Chung Chou, Kuan Cheng Huang
-
Patent number: 11955397Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.Type: GrantFiled: November 9, 2020Date of Patent: April 9, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
-
Patent number: 11953940Abstract: A display apparatus includes a light-transmitting structural plate, some optical microscopic structures, an optical film, a base plate and some light emitting elements. The light-transmitting structural plate has a first side and a second side opposite to each other. The optical microscopic structures are regularly arrayed and formed on the first side or the second side. The optical microscopic structure has an inclined surface connecting at a connecting line and forming an angle ranging between 30 degrees and 150 degrees with a corresponding inclined surface of an adjacent one of the optical microscopic structures. The optical film is located on the first side. The base plate is separated from the second side by a space. The light emitting elements are located inside the space and disposed on the base plate. The light emitting elements respectively emit a light ray to the light-transmitting structural plate.Type: GrantFiled: October 7, 2020Date of Patent: April 9, 2024Assignee: DARWIN PRECISIONS CORPORATIONInventors: Yu-Cheng Chang, Shu-Ching Peng, Yu-Ming Huang
-
Patent number: 11952420Abstract: Provided herein are antibodies, or antigen-binding portions thereof, that specifically bind and inhibit TREM-1 signaling, wherein the antibodies do not bind to one or more Fc?Rs and do not induce the myeloid cells to produce inflammatory cytokines. Also provided are uses of such antibodies, or antigen-binding portions thereof, in therapeutic applications, such as treatment of autoimmune diseases.Type: GrantFiled: September 10, 2021Date of Patent: April 9, 2024Assignee: BRISTOL-MYERS SQUIBB COMPANYInventors: Achal Pashine, Michael L Gosselin, Aaron P. Yamniuk, Derek A. Holmes, Guodong Chen, Priyanka Apurva Madia, Richard Yu-Cheng Huang, Stephen Michael Carl
-
Patent number: 11955191Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.Type: GrantFiled: June 2, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Perng-Fei Yuh, Tung-Cheng Chang, Gu-Huan Li, Chia-En Huang, Chun-Ying Lee, Yih Wang
-
Publication number: 20240109230Abstract: A manufacturing method of housing structure of electronic device is provided. The manufacturing method includes stacking a first structural layer, a painting layer, and a second structural layer, wherein the painting layer is located between the first and the second structural layers. The layer stacked after the painting layer washes and squeezes at least a portion of the flowing painting layer to form a random texture pattern.Type: ApplicationFiled: May 16, 2023Publication date: April 4, 2024Applicants: Acer Incorporated, Nan Pao New Materials (Huaian) Co., Ltd.Inventors: Pin-Chueh Lin, Wen-Chieh Tai, Cheng-Nan Ling, Chang-Huang Huang
-
Publication number: 20240113288Abstract: This application relates to a negative electrode plate, a secondary battery and apparatus thereof. The secondary battery of the present application comprises a negative electrode plate, the negative electrode plate comprises a composite current collector and a negative electrode active material layer disposed on at least one surface of the composite current collector, the negative electrode active material layer comprises a silicon-based active material, the silicon-based active material accounts for 0.5 wt % to 50 wt % of total mass of the negative electrode active material layer, and the composite current collector comprises a polymer support layer and a metal conductive layer disposed on at least one surface of the polymer support layer. The secondary battery and the negative electrode plate achieve good coordination between the current collector and the negative electrode active material layer.Type: ApplicationFiled: November 30, 2023Publication date: April 4, 2024Applicant: Contemporary Amperex Technology Co., LimitedInventors: Cheng LI, Qisen HUANG, Xin LIU, Changliang SHENG, Shiwen WANG, Xianghui LIU, Jia PENG, Mingling LI, Chengdu LIANG
-
Publication number: 20240109995Abstract: A preparation method of solvent-free self-emulsifying water-soluble chlorinated polypropylene is provided. By uniformly mixing chlorinated polypropylene, an acrylic acid/ester mixture and a cosolvent, initiating the chlorinated polypropylene to generate free radicals by using an initiator, further initiating free radical polymerization of the acrylic acid/ester mixture, then adding an isocyanate-terminal carboxyl hyperbranched polyester adduct, reacting, then neutralizing with amine, emulsifying, and diluting with deionized water, the solvent-free self-emulsifying water-soluble chlorinated polypropylene with a solid content of 30-45% may be obtained. The process of the present invention is simple, and easy to industrialize, and the product has the advantages of low VOC content, no organic solvent, water dilution, excellent stability, etc., and is expected to be widely used in the fields of water-soluble paints, surface modification of non-polar or low-polar plastics and the like.Type: ApplicationFiled: November 17, 2023Publication date: April 4, 2024Applicants: WUHAN HYPERBRANCHED POLYMERS SCIENCE & TECHNOLOGY CO., LTD., HUBEI HYPERBRANCHED NEW MATERIALS SCIENCE & TECHNOLOGY CO., LTD.Inventors: Sufang CHEN, Sunmeng HUANG, Yangjie LUO, Cheng XU
-
Publication number: 20240114614Abstract: Disclosed is a thermal conduction-electrical conduction isolated circuit board with a ceramic substrate and a power transistor embedded, mainly comprising: a dielectric material layer, a heat-dissipating ceramic block, a securing portion, a stepped metal electrode layer, a power transistor, and a dielectric material packaging, wherein a via hole is formed in the dielectric material layer, the heat-dissipating ceramic block is correspondingly embedded in the via hole, the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less than that of the dielectric material layer, the stepped metal electrode layer conducts electricity and heat for the power transistor, the dielectric material packaging is configured to partially expose the source connecting pin, drain connecting pin, and gate connecting pin of the encapsulated stepped metal electrode layer.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Inventors: HO-CHIEH YU, CHEN-CHENG-LUNG LIAO, CHUN-YU LIN, JASON AN CHENG HUANG, CHIH-CHUAN LIANG, KUN-TZU CHEN, NAI-HIS HU, LIANG-YO CHEN
-
Publication number: 20240113195Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.Type: ApplicationFiled: February 22, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Ni YU, Lung-Kun CHU, Chun-Fu LU, Chung-Wei HSU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
-
Publication number: 20240110976Abstract: An electronic device and a method for performing clock gating in the electronic device are provided. The electronic device includes at least one function circuit, a device under test (DUT) circuit and at least one gating circuit. The function circuit is configured to operate according to at least one primary clock, and the DUT circuit is configured to operate according to at least one secondary clock. In addition, the clock gating circuit is configured to control whether to enable the primary clock according to at least one primary enable signal, and control whether to enable the secondary clock according to the primary enable signal and a secondary enable signal.Type: ApplicationFiled: October 3, 2023Publication date: April 4, 2024Applicant: Realtek Semiconductor Corp.Inventors: Ching-Feng Huang, Yu-Cheng Lo