Abstract: A method includes: inspecting a reticle in a reticle pod, the reticle pod including a sealed space to accommodate the reticle, and the reticle pod further comprising a window arranged on an upper surface of the reticle pod, wherein the inspecting is performed through the window; and moving the reticle out of the reticle pod for performing a lithography operation using the reticle.

Abstract: A memory socket includes a frame having a base portion and a side portion, and a push-eject locking mechanism in physical communication with the base portion and with the side portion. The push-eject locking mechanism to transition between an unlocked position and a locked position. The push-eject locking mechanism includes an eject bar component and a lever component. The weight of the eject bar component biases the push-eject locking mechanism towards the unlocked position. Based on a force being exerted on the lever component, the lever component pivots and transition the push-eject locking mechanism from the unlocked position to the locked position.

Abstract: A photonic integrated circuit structure includes a semiconductor substrate. A waveguide is disposed above the semiconductor substrate and has an inclined plane. A mirror coating layer is conformally disposed on the inclined plane. A cladding layer covers the waveguide and the mirror coating layer. A hole is disposed in the semiconductor substrate or the cladding layer, and the hole overlaps the inclined plane in a vertical direction. In addition, an optical fiber is disposed in the hole to receive a reflected light from the mirror coating layer.

Abstract: The present disclosure provides the use of an anti-PD-1 antibody in combination with famitinib in the preparation of a drug for treating tumors. In the present technical solution, toxicity is controllable and tolerable. At the same time, the described drug combination effectively reduces adverse reactions to the anti-PD-1 antibody, such as the occurrence of reactive capillary endothelial proliferation.

Abstract: A video decoder may be configured to receive a block of video data that was encoded using a coding mode that includes a search process in one or more reference frames. The video decoder may prefetch reference samples in a fixed search region of at least one reference frame of the one or more reference frames, and decode the block of video data using the coding mode, including performing the search process for the coding mode using the prefetched reference samples.

Abstract: A liquid crystal display (LCD) of the chiral polymer stabilized alignment (C-PSA) mode, a method of its production and its use as an energy-saving display.

Abstract: A heat dissipation assembly is disclosed and includes a fan, a vapor chamber and a heat dissipation fin set. The fan includes a fan frame, an impeller and a fan cover. The impeller is disposed on the fan frame and accommodated in an accommodation space. The impeller includes plural metal blades and a hub, and the plural metal blades are radially arranged on the periphery of the hub to form a dense-metal-blade impeller. The fan cover is assembled with the fan frame to form an outlet, and the fan cover includes an inlet. The vapor chamber includes an upper plate and a lower plate assembled with each other. The upper plate or the lower plate is connected to the fan cover, and the vapor chamber and the fan cover are coplanar. The heat dissipation fin set is connected to the lower plate and spatially corresponding to the outlet.

Abstract: A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.

Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.

Abstract: A power ground noise reduction system includes a bandgap circuit and a noise reduction circuit. The bandgap circuit includes an input terminal for receiving a working voltage, and an output terminal for outputting a bandgap reference voltage. The noise reduction circuit includes a first input terminal coupled to the output terminal of the bandgap circuit for receiving the bandgap reference voltage, a second input terminal for receiving the working voltage, a ground terminal coupled to a low voltage terminal, a first current source for receiving the working voltage received by the second input terminal and generating a first current, and a second current source for generating a second current to the low voltage terminal through the ground terminal.

Abstract: The disclosure herein relates to rechargeable batteries and solid electrolytes therefore which include lithium-stuffed garnet oxides, for example, in a thin film, pellet, or monolith format wherein the density of defects at a surface or surfaces of the solid electrolyte is less than the density of defects in the bulk. In certain disclosed embodiments, the solid-state anolyte, electrolyte, and catholyte thin films, separators, and monoliths consist essentially of an oxide that conducts Li+ ions. In some examples, the disclosure herein presents new and useful solid electrolytes for solid-state or partially solid-state batteries. In some examples, the disclosure presents new lithium-stuffed garnet solid electrolytes and rechargeable batteries which include these electrolytes as separators between a cathode and a lithium metal anode.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: An electronic device is provided. The electronic device includes a frame, a working panel, a case, and an adhesive material. The frame includes a side wall and a back plate. The working panel is disposed on the back plate. The case is disposed on the frame and adjacent to the working panel. The adhesive material is disposed on the case. The side wall has an outer surface facing away from the working panel. In a cross-section view of the electronic device, a portion of the adhesive material is in contact with the outer surface of the side wall of the frame, and a length of the adhesive material is greater than or equal to 50% of a length of the side wall of the frame along an extension direction.

Abstract: A cable arrangement mechanism is provided, which is disposed inside the housing of an electronic device. The cable arrangement mechanism includes a first tube, a second tube, and a plurality of first resilient elements. The first tube includes a first base, a first extension connected to the first base and extending from a first inner surface, and a first extrusion connected to the first base and extending from a first outer surface. The second tube includes a second base, a second extension connected to the second base and extending from a second inner surface, and a second extrusion connected to the second base and extending from a second outer surface. The first resilient elements respectively connect the first extrusion and the second extrusion to the housing, so that the first tube and the second tube are rotatably connected to the housing.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

Abstract: Provided is a fingerprint sensor, including: a substrate; a plurality of photosensitive devices disposed on the substrate; a light-emitting module disposed on a side, distal to the substrate, of the plurality of photosensitive devices; and a protective cover disposed on a side, distal to the substrate, of the light-emitting module, wherein the protective cover is provided with a plurality of conductive structures electrically connected to the light-emitting module, the plurality of conductive structures being in one-to-one correspondence with the plurality of photosensitive devices, and an orthographic projection of each conductive structure onto the substrate at least partially being overlapped with an orthographic projection of the photosensitive device corresponding to the conductive structure onto the substrate.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: A semiconductor device includes: a substrate; a channel layer disposed on the substrate, wherein the channel layer is made of GaN; a barrier layer disposed on the channel layer, wherein the barrier layer is made of AlzGa1-zN; and an inserting structure inserted between the channel layer and the barrier layer. The inserting structure includes: a first inserting layer disposed on the channel layer, wherein the first inserting layer is made of AlxGa1-xN; and a second inserting layer disposed on the first inserting layer, wherein the second inserting layer is made of AlyGa1-yN, and y is greater than x. The semiconductor device further includes: a gate electrode disposed on the barrier layer; a source electrode and a drain electrode disposed on the barrier layer and respectively at opposite sides of the gate electrode; and a spike region formed below at least one of the source electrode and the drain electrode.

Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.