Patents by Inventor Cheng Huang

Cheng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240113195
    Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.
    Type: Application
    Filed: February 22, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Ni YU, Lung-Kun CHU, Chun-Fu LU, Chung-Wei HSU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20240114614
    Abstract: Disclosed is a thermal conduction-electrical conduction isolated circuit board with a ceramic substrate and a power transistor embedded, mainly comprising: a dielectric material layer, a heat-dissipating ceramic block, a securing portion, a stepped metal electrode layer, a power transistor, and a dielectric material packaging, wherein a via hole is formed in the dielectric material layer, the heat-dissipating ceramic block is correspondingly embedded in the via hole, the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less than that of the dielectric material layer, the stepped metal electrode layer conducts electricity and heat for the power transistor, the dielectric material packaging is configured to partially expose the source connecting pin, drain connecting pin, and gate connecting pin of the encapsulated stepped metal electrode layer.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: HO-CHIEH YU, CHEN-CHENG-LUNG LIAO, CHUN-YU LIN, JASON AN CHENG HUANG, CHIH-CHUAN LIANG, KUN-TZU CHEN, NAI-HIS HU, LIANG-YO CHEN
  • Patent number: 11946733
    Abstract: An image rendering device and an image rendering method are disclosed. For the elements of the image rendering device, a first sensor and a second sensor are configured to sense a target object in a two-dimensional (2D) mode and three-dimensional (3D) mode to generate a first surface-color-signal, a first 3D-depth-signal, a second surface-color-signal and a second 3D-depth-signal respectively. An IR projector is configured to generate an IR-dot-pattern. A processor is configured to control the IR projector to project the IR-dot-pattern on the target object in the 3D mode, and configured to process the first surface-color-signal, the second surface-color-signal, the first 3D-depth-signal and the second 3D-depth-signal to obtain a color 3D model of the target object.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: April 2, 2024
    Assignee: EYS3D MICROELECTRONICS CO.
    Inventors: Kuan-Cheng Chung, Tsung-Yi Huang, Shi-Fan Chang
  • Patent number: 11947150
    Abstract: A backlit-module-embedded illuminated keyswitch structure includes a baseplate, a mask film disposed below the baseplate and having a first coating configured to substantially reflect a light, a light guide sheet disposed at one side of the mask film and having a light source hole, a reflective layer disposed at one side of the light guide sheet opposite to the mask film and having an opening communicating with the light source hole, a top glue configured to connect the mask film and the light guide sheet around the light source hole, and a bottom glue configured to connect the light guide sheet and the reflective layer around the light source hole. The first coating covers the light source hole. In a stacked direction of the mask film, the light guide sheet, and the reflective layer, at least one of the top glue and the bottom glue overlaps the first coating.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: April 2, 2024
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Heng-Yi Huang, Hsin-Cheng Ho, Po-Yueh Chou
  • Patent number: 11948016
    Abstract: Embodiments of the present invention relate to a method, system and computer program product for application programming interface (API) management. According to the method, in response to a first response from an API provider indicating a failure of a first API request initiated by an API requestor, a second API request is generated at least based on the first API request. The second API request is transmitted to the API provider. A second response to the second API request is received from the API provider. A third response is provided to the API requestor based on the second response.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: April 2, 2024
    Assignee: International Business Machines Corporation
    Inventors: Yun Fei Yuan, Qun Pan, Zhun Huang, Xiang Juan Meng, Cheng Fang Wang
  • Patent number: 11948796
    Abstract: One or more embodiments described herein relate to selective methods for fabricating devices and structures. In these embodiments, the devices are exposed inside the process volume of a process chamber. Precursor gases are flowed in the process volume at certain flow ratios and at certain process conditions. The process conditions described herein result in selective epitaxial layer growth on the {100} planes of the crystal planes of the devices, which corresponds to the top of each of the fins. Additionally, the process conditions result in selective etching of the {110} plane of the crystal planes, which corresponds to the sidewalls of each of the fins. As such, the methods described herein provide a way to grow or etch epitaxial films at different crystal planes. Furthermore, the methods described herein allow for simultaneous epitaxial film growth and etch to occur on the different crystal planes.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: April 2, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yi-Chiau Huang, Chen-Ying Wu, Abhishek Dube, Chia Cheng Chin, Saurabh Chopra
  • Patent number: 11948987
    Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11949051
    Abstract: A wavelength conversion member includes a substrate, a phosphor layer, and a ventilated blade. The substrate is configured to rotate based on an axis. The phosphor layer is disposed on the substrate. The ventilated blade is disposed on the substrate and has a pore density between 10 ppi and 500 ppi or a volume porosity between 5% and 95%.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: April 2, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yen-I Chou, Jih-Chi Li, Wen-Cheng Huang
  • Patent number: 11948581
    Abstract: A smart interpreter engine is provided. The smart interpreter engine includes a speech to text converter, a natural language processing module and a translator. The speech to text converter is utilized for converting speech data corresponding to a first language into text data corresponding to the first language. The natural language processing module is utilized for converting the text data corresponding to the first language into glossary text data corresponding to the first language according to a game software. The translator is utilized for converting the glossary text data corresponding to the first language into text data corresponding to a second language.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: April 2, 2024
    Assignee: ACER INCORPORATED
    Inventors: Gianna Tseng, Shih-Cheng Huang, Shang-Yao Lin, Szu-Ting Chou
  • Publication number: 20240105546
    Abstract: A module device on a first substrate includes a power module, a housing, a pair of locking structures. The housing covers the power module. The locking structures are installed on a pair of opposite sides of the housing, and the locking structure includes a main body, a locking ring, a pair of ribs and anchoring portions. The locking ring extends from a side toward an inner side of the main body, and is a double-ring structure, which includes an inner and an outer ring. A first side of the outer ring is connected to the main body, a second side of the outer ring is connected to the inner ring. The ribs extend along a normal direction of the top surface of the main body. The anchoring portions are disposed at the end of the ribs, and an extending direction is perpendicular to an extending direction of the rib.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 28, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Ji-Yuan Syu, Yuan-Cheng Huang, Yu-Chih Wang
  • Publication number: 20240102959
    Abstract: An IC structure includes a biologically sensitive field-effect transistor (BioBET) in a semiconductor substrate, and a dielectric layer over a backside surface of the semiconductor substrate. The dielectric layer has a sensing well extending through the dielectric layer to a channel region of the BioFET. The IC structure further includes a biosensing film, a plurality of fluid channel walls, and a first heater. The biosensing film lines the sensing well in the dielectric layer. The fluid channel walls are over the biosensing film and define a fluid containment region over the sensing well of the dielectric layer. The first heater is in the semiconductor substrate. The first heater has at least a portion overlapping with the fluid containment region.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Tsun CHEN, Yi-Hsing HSIAO, Jui-Cheng HUANG, Yu-Jie HUANG
  • Publication number: 20240106040
    Abstract: A cover plate of a cylindrical battery and the cylindrical battery are provided by the present application. The cover plate of the cylindrical battery includes a pole column. A bottom of the pole column is connected with a current collecting plate. The pole column is sleeved with a sealing ring. A first insulating element and a cover slip are sequentially sleeved on an outside of the sealing ring along a vertical direction. The first insulating element insulates the current collecting plate from the cover slip.
    Type: Application
    Filed: October 21, 2022
    Publication date: March 28, 2024
    Applicant: EVE POWER CO., LTD.
    Inventors: Haixu Lu, He Zhao, Liming Huang, Cheng Yang, Yuebin Xu, Wei He
  • Patent number: 11938405
    Abstract: An electronic device and a method for detecting abnormal device operation are provided. The method includes: obtaining multiple action events of a movable input device, and each action event including a relative coordinate and a time stamp of the movable input device; generating multiple absolute coordinates based on the relative coordinate of each action event; estimating multiple speed vectors based on the absolute coordinates and the time stamp of each action event; estimating multiple acceleration vectors based on the speed vectors and the time stamp of each action event; and estimating a probability of abnormal operation based on the speed vectors and the acceleration vectors.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: March 26, 2024
    Assignee: Acer Incorporated
    Inventors: Tien-Yi Chi, Wei-Chieh Chen, Shih-Cheng Huang, Tzu-Lung Chuang
  • Patent number: 11942478
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Guan-Lin Chen
  • Patent number: 11940412
    Abstract: A biosensor system includes an array of biosensors with a plurality of electrodes situated proximate the biosensor. A controller is configured to selectively energize the plurality of electrodes to generate a DEP force to selectively position a test sample relative to the array of biosensors.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jie Huang, Jui-Cheng Huang, Yi-Hsing Hsiao
  • Patent number: 11942377
    Abstract: A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Wei-Hao Wu, Kuo-Cheng Chiang
  • Patent number: 11942513
    Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Jui-Chien Huang
  • Publication number: 20240091893
    Abstract: A mounting frame for being mounted with either one of first and second screwdrivers, includes a main frame, a mounting seat, and first and second mounting plates. The mounting seat has a plate attachment hole set. The first mounting plate has a first seat attachment hole set operable to be connected to the plate attachment hole set, and a first driver attachment hole set for the first screwdriver to be attached thereto. The second mounting plate has a second seat attachment hole set operable to be connected to the plate attachment hole set, and a second driver attachment hole set for the second screwdriver to be attached thereto.
    Type: Application
    Filed: August 16, 2023
    Publication date: March 21, 2024
    Applicant: Jabil Inc.
    Inventors: Harpuneet Singh, Lei Hu, Ying-Chieh Huang, Wei-Hsiu Hsieh, Xiao-Ting Zheng, Chien-Cheng Chu
  • Publication number: 20240093373
    Abstract: A method for preparing antibacterial stainless steel by surface alloying includes the steps of coating an infiltration promoter layer on a stainless steel surface, coating an antibacterial metal layer on a surface of the infiltration promoter layer, and performing heat treatment of the stainless steel to diffuse an antibacterial metal into the stainless steel. This method can be applied to various types of stainless steel, and the antibacterial metal can be diffused and quenched into the stainless steel, such that the finally formed surface of the stainless steel has an antibacterial alloy layer with a specific thickness to provide better corrosion resistance and antibacterial ability without changing the advantages and properties of the antibacterial metal or stainless steel substrate, and the thickness and concentration of the antibacterial metal layer, and the parameters for heat treatment can be adjusted to control the chemical composition and thickness of the antibacterial alloy layer.
    Type: Application
    Filed: November 16, 2022
    Publication date: March 21, 2024
    Inventors: WEN-TA TSAI, BERNARD HAOCHIH LIU, ZHI-YAN CHEN, CHONG-CHENG HUANG
  • Patent number: D1020049
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: March 26, 2024
    Inventors: Dongjun Ding, Cheng Gong, Weifeng Huang, Wenlong Wu