Abstract: A method includes the operations below. A first and second layout patterns corresponding to a first and second area are placed. Third layout patterns corresponding to a first continuous fin over the first area and second area, and corresponding to a second fin including separate portions spaced apart by a first recess over the first area are placed. A fourth layout pattern, corresponding to a dummy gate, at the recess portion and between the first layout pattern and the second layout pattern, is placed to generate a layout design of a semiconductor device. A side of the second area facing the first recess is substantially flat, and the semiconductor device is fabricated by a tool based on the layout design. A first length of the first continuous fin is equal to a sum of a second length of the second fin and a third length of the first recess.

Abstract: A semiconductor device includes a substrate and fins. The fins are formed on a first area and a second area of the substrate. The first area includes a first recess. The second area is located with respect to the first area. The first recess is disposed at a side of the first area, and faces the second area. A projection area of the first recess on a side of the second area is substantially flat.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method is performed by forming a gate structure over a substrate, and selectively implanting the substrate according to the gate structure to form first and second source/drain regions on opposing sides of the gate structure. A first MEOL structure is formed on the first source/drain region and a second MEOL structure is formed on the second source/drain region. The first MEOL structure has a bottommost surface that extends in a first direction from directly over the first source/drain region to laterally past an outermost edge of the first source/drain region. A conductive structure is formed to contact the first MEOL structure and the second MEOL structure. The conductive structure laterally extends from directly over the first MEOL structure to directly over the second MEOL structure along a second direction perpendicular to the first direction.

Abstract: A semiconductor device includes first and second transistors, a pair of first source/drain regions, a pair of second source/drain regions, and a cell. Each of the first source/drain regions corresponds to a first source/drain terminal of a respective one of the first and second transistors. Each of the second source/drain regions corresponds to a second source/drain terminal of a respective one of the first and second transistors. The cell includes a first voltage rail, a pair of second voltage rails, and a cell circuit. The first voltage rail is coupled to the first source/drain regions. Each of the second voltage rails is coupled to a respective one of the second source/drain regions and is configured to be coupled to the first voltage rail. The cell circuit is coupled to one of the second voltage rails.

Abstract: An integrated circuit structure includes a set of rails, a first and second set of conductive structures and a first set of vias. The set of rails extends in a first direction and is located at a first level. Each rail of the set of rails is separated from one another in a second direction. The first set of conductive structures extends in the second direction, overlaps the set of rails and is located at a second level. The first set of vias is between the set of rails and the first set of conductive structures. Each of the first set of vias is located where each of the first set of conductive structures overlaps each of the set of rails. The first set of vias couple the first set of conductive structures to the set of rails. The second set of conductive structures is between the set of rails.

Abstract: A semiconductor device includes first and second transistors, a pair of first source/drain regions, a pair of second source/drain regions, and a cell. Each of the first source/drain regions corresponds to a first source/drain terminal of a respective one of the first and second transistors. Each of the second source/drain regions corresponds to a second source/drain terminal of a respective one of the first and second transistors. The cell includes a first voltage rail, a pair of second voltage rails, and a cell circuit. The first voltage rail is coupled to the first source/drain regions. Each of the second voltage rails is coupled to a respective one of the second source/drain regions and is configured to be coupled to the first voltage rail. The cell circuit is coupled to one of the second voltage rails.

Abstract: A semiconductor device includes a substrate and fins. The fins are formed on a first area and a second area of the substrate. The first area includes a first recess. The second area is located with respect to the first area. The first recess is disposed at a side of the first area, and faces the second area. A projection area of the first recess on a side of the second area is substantially flat.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) having parallel conductive paths between a BEOL interconnect layer and a middle-end-of-the-line (MEOL) structure, which are configured to reduce a parasitic resistance and/or capacitance of the IC. The IC comprises source/drain regions arranged within a substrate and separated by a channel region. A gate structure is arranged over the channel region and a MEOL structure is arranged over one of the source/drain regions. A conductive structure is arranged over and in electrical contact with the MEOL structure. A first conductive contact is arranged between the MEOL structure and an overlying BEOL interconnect wire (e.g., a power rail). A second conductive contact is configured to electrically couple the BEOL interconnect wire and the MEOL structure along a conductive path extending through the conductive structure, thereby forming parallel conductive paths between the BEOL interconnect layer and the MEOL structure.

Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.

Abstract: A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary pattern therebetween. The first boundary pattern is exchanged with a second boundary pattern based on a number or positions of signal wires in the first boundary pattern. A cell layout for use in a patterning process can then be determined, the cell layout including the second boundary pattern.

Abstract: A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

Abstract: A method of generating a netlist comprises extracting a first capacitance value between the first set of electrical components inside a defined region using a first extraction technique. The method additionally comprises extracting a second capacitance value between a second set of electrical components comprising at least one electrical component outside the defined region using a second extraction technique different from the first extraction technique. The method also comprises generating the netlist including the first capacitance value and the second capacitance value. The first extraction technique is capable of extracting capacitance values between electrical components arranged in a first quantity of directions with respect to one another and the second extraction technique is capable of extracting capacitance values between electrical components arranged in a second quantity of directions with respect to one another. The first quantity of directions is greater than the second quantity of directions.

Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.

Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.

Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.

Abstract: A method of generating a netlist comprises extracting a first capacitance value between the first set of electrical components inside a defined region using a first extraction technique. The method additionally comprises extracting a second capacitance value between a second set of electrical components comprising at least one electrical component outside the defined region using a second extraction technique different from the first extraction technique. The method also comprises generating the netlist including the first capacitance value and the second capacitance value. The first extraction technique is capable of extracting capacitance values between electrical components arranged in a first quantity of directions with respect to one another and the second extraction technique is capable of extracting capacitance values between electrical components arranged in a second quantity of directions with respect to one another. The first quantity of directions is greater than the second quantity of directions.

Abstract: A semiconductor device design method performed by at least one processor comprises extracting, using a resistance and capacitance (RC) extraction tool, at least one first parasitic capacitance among electrical components inside one or more regions of a plurality of regions in a layout of a semiconductor device. The method also comprises extracting, using the RC extraction tool, at least one second parasitic capacitance among electrical components outside the regions of the plurality of regions. The method further comprises combining, using a netlist generator tool, the extracted first and second parasitic capacitances into a netlist representing the layout. The RC extraction tool is configured to extract the first parasitic capacitances inside at least one region of the plurality of regions using a methodology more accurate than that for extracting the second parasitic capacitances.

Abstract: Among other things, one or more systems and techniques for generating or implementing a hybrid design rule set are provide herein. A set of color design rules and a set of color agnostic design rules are generated and exposed for selective design rule assignment. In an embodiment, a first color design rule is assigned to a first polygon. In an embodiment, a first color agnostic design rule is assigned to a second polygon. In this way, color design rules and color agnostic design rules are selectively applied to polygons of a design layout. Color design rules are selected for space and design efficiency. Color agnostic rules are selected for conservative design layout for design ease. A design rule checking stage and a design rule fixing stage are performed such that the design layout is compliant after color decomposition without a second design rule fixing stage.

Abstract: Among other things, one or more systems and techniques for generating or implementing a hybrid design rule set are provide herein. A set of color design rules and a set of color agnostic design rules are generated and exposed for selective design rule assignment. In an embodiment, a first color design rule is assigned to a first polygon. In an embodiment, a first color agnostic design rule is assigned to a second polygon. In this way, color design rules and color agnostic design rules are selectively applied to polygons of a design layout. Color design rules are selected for space and design efficiency. Color agnostic rules are selected for conservative design layout for design ease. A design rule checking stage and a design rule fixing stage are performed such that the design layout is compliant after color decomposition without a second design rule fixing stage.

Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.