Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.

Abstract: A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary pattern therebetween. The first boundary pattern is exchanged with a second boundary pattern based on a number or positions of signal wires in the first boundary pattern. A cell layout for use in a patterning process can then be determined, the cell layout including the second boundary pattern.

Abstract: A semiconductor device design method performed by at least one processor comprises extracting, using a resistance and capacitance (RC) extraction tool, at least one first parasitic capacitance among electrical components inside one or more regions of a plurality of regions in a layout of a semiconductor device. The method also comprises extracting, using the RC extraction tool, at least one second parasitic capacitance among electrical components outside the regions of the plurality of regions. The method further comprises combining, using a netlist generator tool, the extracted first and second parasitic capacitances into a netlist representing the layout. The RC extraction tool is configured to extract the first parasitic capacitances inside at least one region of the plurality of regions using a methodology more accurate than that for extracting the second parasitic capacitances.

Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.

Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.

Abstract: In a semiconductor device design method performed by at least one processor, at least one first parasitic parameter between electrical components inside a region of a layout of a semiconductor device and at least one second parasitic parameter between electrical components outside the region of the layout are extracted by different tools. The extracted parasitic parameters are incorporated into the layout.

Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.

Abstract: The present disclosure relates to a method and apparatus for accurate RC extraction. A pattern database is configured to store layout patterns and their associated 3D extraction parameters. A pattern-matching tool is configured to partition a design into a plurality of patterns, and to search the pattern database for a respective pattern and associated 3D extraction parameters. If the respective pattern is already stored in the pattern database, then the associated 3D extraction parameters stored in the database are assigned to the respective pattern without the need to extract the respective pattern. If the respective pattern is not stored in the pattern database, then the extraction tool extracts the pattern and stores its associated 3D extraction parameters in the pattern database for future use. In this manner a respective pattern is extracted only once for a given design or plurality of designs.

Abstract: A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a non-UV tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the non-UV tape and marks a pattern on the second surface of the wafer. According to the laser-marking method of the embodiment, the pattern is formed by the non-UV residuals left on the second surface of the wafer, and the components of the glue residuals at least include elements of silicon and carbon.

Abstract: The present disclosure relates to a method and apparatus for accurate RC extraction. A pattern database is configured to store layout patterns and their associated 3D extraction parameters. A pattern-matching tool is configured to partition a design into a plurality of patterns, and to search the pattern database for a respective pattern and associated 3D extraction parameters. If the respective pattern is already stored in the pattern database, then the associated 3D extraction parameters stored in the database are assigned to the respective pattern without the need to extract the respective pattern. If the respective pattern is not stored in the pattern database, then the extraction tool extracts the pattern and stores its associated 3D extraction parameters in the pattern database for future use. In this manner a respective pattern is extracted only once for a given design or plurality of designs.

Abstract: An embodiment method of streamlining parasitic modeling using a common device profile includes importing, using a processor, a simulated middle end of line (MEOL) profile into a characterization tool, generating, using the processor, a MEOL pattern based on the simulated MEOL profile, import, using the processor, the MEOL pattern and a real profile into a field solver to generate a MEOL capacitance table, updating, using the processor, capacitance data in the characterization tool based on the MEOL capacitance table generated, and generating, using the processor, a resistance and capacitance parasitic extraction technology file using the characterization tool with the capacitance data as updated.

Abstract: In a semiconductor device design method performed by at least one processor, at least one first parasitic parameter between electrical components inside a region of a layout of a semiconductor device and at least one second parasitic parameter between electrical components outside the region of the layout are extracted by different tools. The extracted parasitic parameters are incorporated into the layout.

Abstract: Methods for optimizing conductor patterns for conductors formed by ECP and CMP processes. A method includes receiving layout data for an IC design where electrochemical plating (ECP) processes form patterned conductors in at least one metal layer over a semiconductor wafer; determining from the received layout data a global effects factor corresponding to a global pattern density; determining layout effects factors for unit grid areas corresponding to the pattern density of the at least one metal layer within the unit grid areas, determining local effects factors for each unit grid area; using a computing device, executing an ECP simulator using at least one of the global effects factor and the local effects factors, and using the layout effects factor; outputting an predicted post-ECP hump data map from the ECP simulator; and if indicated by a threshold comparison, modifying the layout data.

Abstract: A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

Abstract: A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

Abstract: A semiconductor device structure for a three-dimensional integrated circuit has a semiconductor substrate having a plurality of through-substrate vias provided in the substrate, wherein three or more of the plurality of through-substrate vias are arranged in a hexagonal packing array with respect to their design-rule circle.

Abstract: A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

Abstract: A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a non-UV tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the non-UV tape and marks a pattern on the second surface of the wafer. According to the laser-marking method of the embodiment, the pattern is formed by the non-UV residuals left on the second surface of the wafer, and the components of the glue residuals at least include elements of silicon and carbon.

Abstract: A method of thinning wafer is disclosed. A wafer has an active surface and a back surface is provided. A plurality of protruding components may be disposed on the active surface. The wafer is placed in a mold and a polymeric material is formed in the mold to cover at least the active surface of the wafer. The polymeric material is cured and the mold is removed. The back surface of the wafer is ground to thin the wafer. The polymeric material is removed to expose the active surface of the wafer and the protruding components disposed on the active surface. The polymeric material is allowed to cover the active surface of the wafer and the protruding components through the mold; accordingly, the stress produced during the grinding can be distributed uniformly on the wafer, and the wafer warpage, breakage, or collapse, or the protruding component peeling can be avoided.

Abstract: A method for forming an electric device having power switches around a logic circuit including: forming a logic circuit on a substrate; forming a plurality of power switches around the logic circuit; and coupling first ends of the power switches to a voltage end, and coupling second ends of the power switches to a power receiver of the logic circuit.