Patents by Inventor Cheng-Lin Huang

Cheng-Lin Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250046673
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.
    Type: Application
    Filed: October 22, 2024
    Publication date: February 6, 2025
    Inventors: Shao-Kuan Lee, Cherng-Shiaw Tsai, Ting-Ya Lo, Cheng-Chin Lee, Chi-Lin Teng, Kai-Fang Cheng, Hsin-Yen Huang, Hsiao-Kang Chang, Shau-Lin Shue
  • Patent number: 12183709
    Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.
    Type: Grant
    Filed: December 18, 2023
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Yao Yang, Ling-Wei Li, Yu-Jui Wu, Cheng-Lin Huang, Chien-Chen Li, Lieh-Chuan Chen, Che-Jung Chu, Kuo-Chio Liu
  • Publication number: 20240387422
    Abstract: A semiconductor structure is provided. The semiconductor structure includes an interconnection structure, a passivation layer and a dielectric capping layer. The interconnect structure has a conductive pad located at a top of the interconnection structure. The passivation layer is disposed on the interconnection structure. The passivation layer has a first opening to expose a portion of the conductive pad. The dielectric capping layer is conformally formed on the passivation layer and extends into the first opening. The dielectric capping layer has a second opening to expose the portion of the conductive pad.
    Type: Application
    Filed: April 17, 2024
    Publication date: November 21, 2024
    Inventors: Cheng-Lin HUANG, Ting-Li YANG
  • Publication number: 20240363398
    Abstract: A semiconductor die is provided. The semiconductor die includes a substrate having a front surface, a rear surface opposite to the front surface, and a sidewall connected between the front surface and the rear surface. The sidewall includes a first primary segment immediately connected to the front surface, a second primary segment immediately connected to the rear surface, and a middle segment between the first primary segment and the second primary segment. The slope of the second primary segment is less than the slope of the first primary segment, and the slope of the middle segment is less than the slope of the second primary segment. Each of the first primary segment, the second primary segment, and the middle segment is a flat surface having a slope greater than 0 degrees relative to a line parallel to the front surface of the substrate.
    Type: Application
    Filed: July 5, 2024
    Publication date: October 31, 2024
    Inventors: Yu-Sheng TANG, Fu-Chen CHANG, Cheng-Lin HUANG, Wen-Ming CHEN, Chun-Yen LO, Kuo-Chio LIU
  • Publication number: 20240353241
    Abstract: A platform through-beam sensor device includes a transmitter module and a receiver module. A light emitted by a light-emitting element of the transmitter module is shaped into a light pattern range by a transmitter mask. A range of the light received by a light-receiving element of the receiver module is changed to a receiving range by a receiver mask. When the present invention is used, the transmitter module and the receiver module are respectively installed on two ends of a mechanical apparatus that move relative to each other. After determining a safety range of the relative movement of the two ends, a state that the light-receiving element falls into the light pattern range and the light-emitting element falls into the receiving range is set to be within the safety range. Upon exceeding the safety range, a flying platform is controlled to stop, thereby improving the safety of the flying platform.
    Type: Application
    Filed: August 25, 2023
    Publication date: October 24, 2024
    Applicant: Brogent Technologies Inc.
    Inventors: GUO-SEN LIAN, SHAO-HUA TSAI, CHENG-LIN HUANG, CHIH-HUANG WANG
  • Patent number: 12087618
    Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing the semiconductor wafer with a first dicing blade to form a first opening. The semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape. The first opening is formed in the upper portion of the substrate. The method also includes sawing the semiconductor wafer with a second dicing blade from the first opening to form a second opening under the first opening and in the middle portion of the substrate. The method further includes sawing the semiconductor wafer with a third dicing blade from the second opening to form a third opening under the second opening and penetrating the lower portion of the substrate, so that the semiconductor wafer is divided into two dies. The first dicing blade, the second dicing blade, and the third dicing blade have different widths.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Sheng Tang, Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen, Chun-Yen Lo, Kuo-Chio Liu
  • Publication number: 20240203857
    Abstract: A package structure is provided. The package structure includes a conductive structure having a first portion with a first sidewall and a second portion with a second sidewall, and the first sidewall and the second sidewall have different slopes. The package structure also includes a semiconductor chip beside the conductive structure and a protective layer laterally surrounding the conductive structure and the semiconductor chip. The protective layer covers the first sidewall of the first portion and the second sidewall of the second portion. The protective layer is made of a polymer material dispersed with fillers.
    Type: Application
    Filed: February 28, 2024
    Publication date: June 20, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ling-Wei LI, Jung-Hua CHANG, Cheng-Lin HUANG
  • Publication number: 20240120313
    Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Inventors: Sheng-Yao YANG, Ling-Wei LI, Yu-Jui WU, Cheng-Lin HUANG, Chien-Chen LI, Lieh-Chuan CHEN, Che-Jung CHU, Kuo-Chio LIU
  • Patent number: 11948876
    Abstract: A package structure is provided. The package structure includes a conductive structure having a first portion and a second portion, and the second portion is wider than the first portion. The package structure also includes a semiconductor chip laterally separated from the conductive structure. The package structure further includes a protective layer laterally surrounding the conductive structure and the semiconductor chip. The first portion of the conductive structure has a sidewall extending from the second portion to a surface of the protective layer. The protective layer laterally surrounds an entirety of the sidewall of the first portion.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ling-Wei Li, Jung-Hua Chang, Cheng-Lin Huang
  • Publication number: 20240096642
    Abstract: Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 ?. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Jing-Cheng Lin, Cheng-Lin Huang
  • Publication number: 20240088090
    Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer. The conductive pad has a first portion passing through the insulating layer and the barrier layer and connected to the conductive via structure. The chip package structure includes a conductive bump over the conductive pad. The chip package structure includes a second substrate. The chip package structure includes an underfill layer between the first substrate and the second substrate.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ling-Wei LI, Jung-Hua CHANG, Cheng-Lin HUANG
  • Patent number: 11855039
    Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and having a first portion and a second portion. The chip package structure includes a conductive bump over the second portion of the conductive pad. A third portion of the conductive pad is between the conductive bump and the conductive via structure from a top view of the conductive pad, the conductive bump, and the conductive via structure.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ling-Wei Li, Jung-Hua Chang, Cheng-Lin Huang
  • Patent number: 11854826
    Abstract: Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 ?. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Cheng-Lin Huang
  • Patent number: 11848302
    Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Yao Yang, Ling-Wei Li, Yu-Jui Wu, Cheng-Lin Huang, Chien-Chen Li, Lieh-Chuan Chen, Che-Jung Chu, Kuo-Chio Liu
  • Publication number: 20230369115
    Abstract: A package structure includes a first semiconductor die having a first conductive pad and a second semiconductor die having a second conductive pad. The package structure also includes a conductive structure and a third semiconductor die. The third semiconductor die extends across a portions of the first semiconductor die and the second semiconductor die. A third conductive pad and a fourth conductive pad of the third semiconductor die are aligned with the first conductive pad and the second conductive pad, respectively. The package structure further includes a protective layer surrounding the conductive structure and the third semiconductor die and an insulating layer extending across an interface between the protective layer and the conductive structure. The package structure includes a conductive layer electrically connected to the conductive structure. The conductive layer has a first portion spaced from the conductive structure and a second portion directly above the conductive structure.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ling-Wei LI, Jung-Hua CHANG, Cheng-Lin HUANG
  • Patent number: 11784091
    Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes forming a protective layer to surround the conductive structure and the semiconductor die. The method further includes forming an insulating layer over the protective layer. The insulating layer has an opening exposing a portion of the conductive structure. In addition, the method includes forming a conductive layer over the insulating layer. The conductive layer fills the opening, and the conductive layer has a substantially planar top surface.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ling-Wei Li, Jung-Hua Chang, Cheng-Lin Huang
  • Publication number: 20230154838
    Abstract: A package structure is provided. The package structure includes a conductive structure having a first portion and a second portion, and the second portion is wider than the first portion. The package structure also includes a semiconductor chip laterally separated from the conductive structure. The package structure further includes a protective layer laterally surrounding the conductive structure and the semiconductor chip. The first portion of the conductive structure has a sidewall extending from the second portion to a surface of the protective layer. The protective layer laterally surrounds an entirety of the sidewall of the first portion.
    Type: Application
    Filed: January 20, 2023
    Publication date: May 18, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ling-Wei LI, Jung-Hua CHANG, Cheng-Lin HUANG
  • Publication number: 20230113265
    Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 13, 2023
    Inventors: Sheng-Yao YANG, Ling-Wei LI, Yu-Jui WU, Cheng-Lin HUANG, Chien-Chen LI, Lieh-Chuan CHEN, Che-Jung CHU, Kuo-Chio LIU
  • Patent number: 11569159
    Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a conductive structure over a carrier substrate. The conductive structure has a lower portion and an upper portion, and the upper portion is wider than the lower portion. The method also includes disposing a semiconductor die over the carrier substrate. The method further includes forming a protective layer to surround the conductive structure and the semiconductor die. In addition, the method includes forming a conductive bump over the conductive structure. The lower portion of the conductive structure is between the conductive bump and the upper portion of the conductive structure.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ling-Wei Li, Jung-Hua Chang, Cheng-Lin Huang
  • Patent number: 11545463
    Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Yao Yang, Ling-Wei Li, Yu-Jui Wu, Cheng-Lin Huang, Chien-Chen Li, Lieh-Chuan Chen, Che-Jung Chu, Kuo-Chio Liu