Patents by Inventor Cheng-Lin Huang

Cheng-Lin Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180033747
    Abstract: An embodiment is a structure including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer extends through the first dielectric layer to contact the contact pad. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer. A second metallization layer is formed overlying the second dielectric layer and extends through the second dielectric layer to contact the first metallization layer.
    Type: Application
    Filed: October 6, 2017
    Publication date: February 1, 2018
    Inventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang
  • Publication number: 20180033695
    Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.
    Type: Application
    Filed: December 9, 2016
    Publication date: February 1, 2018
    Inventors: Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen
  • Patent number: 9881908
    Abstract: An embodiment package includes a first package; a thermal interface material (TIM) contacting a top surface of the first package, and a second package bonded to the first package. The second package includes a first semiconductor die, and the TIM contacts a bottom surface of the first semiconductor die. The package further includes a heat spreader disposed on an opposing surface of the second package as the first package.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Yi Lin, Hsien-Wen Liu, Po-Yao Lin, Cheng-Lin Huang, Shyue-Ter Leu, Shin-Puu Jeng
  • Patent number: 9875979
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Publication number: 20180019183
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a first package structure including a first semiconductor die that has a first side and a second side opposite thereto. The chip package also includes a package layer partially or completely encapsulating the first semiconductor die, and a conductive feature in the package layer. The chip package further includes a first heat-spreading layer over the first side of the first semiconductor die and a first cap layer on the first heat-spreading layer.
    Type: Application
    Filed: July 14, 2016
    Publication date: January 18, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Hua WANG, Po-Yao LIN, Shu-Shen YEH, Kuang-Chun LEE, Shin-Puu JENG, Shyue-Ter LEU, Cheng-Lin HUANG, Hsiu-Mei YU
  • Patent number: 9870975
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a first package structure including a first semiconductor die that has a first side and a second side opposite thereto. The chip package also includes a package layer partially or completely encapsulating the first semiconductor die, and a conductive feature in the package layer. The chip package further includes a first heat-spreading layer over the first side of the first semiconductor die and a first cap layer on the first heat-spreading layer.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Hua Wang, Po-Yao Lin, Shu-Shen Yeh, Kuang-Chun Lee, Shin-Puu Jeng, Shyue-Ter Leu, Cheng-Lin Huang, Hsiu-Mei Yu
  • Patent number: 9824989
    Abstract: An embodiment is a package including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound and the chip and has a first opening exposing the contact pad. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer fills the first opening. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer and has a second opening over the first opening. A second metallization layer is formed overlying the second dielectric layer and formed in the second opening.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: November 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang
  • Publication number: 20170317044
    Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: Jung-Hua Chang, Cheng-Lin Huang, Jing-Cheng Lin
  • Patent number: 9748156
    Abstract: A semiconductor package includes a cover, a substrate, at least one semiconductor device and at least one corner stiffener. The cover has at least one corner portion. The substrate is in force communication with the cover. The substrate has at least one corner portion. The semiconductor device is present between the cover and the substrate. The corner stiffener is present on at least one of the corner portion of the cover and the corner portion of the substrate.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: August 29, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Shen Yeh, Cheng-Lin Huang, Chin-Hua Wang, Kuang-Chun Lee, Wen-Yi Lin, Ming-Chih Yew, Yu-Huan Chen, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng
  • Publication number: 20170207204
    Abstract: An embodiment package includes a first package; a thermal interface material (TIM) contacting a top surface of the first package, and a second package bonded to the first package. The second package includes a first semiconductor die, and the TIM contacts a bottom surface of the first semiconductor die. The package further includes a heat spreader disposed on an opposing surface of the second package as the first package.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 20, 2017
    Inventors: Wen-Yi Lin, Hsien-Wen Liu, Po-Yao Lin, Cheng-Lin Huang, Shyue-Ter Leu, Shin-Puu Jeng
  • Patent number: 9711475
    Abstract: A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Cheng-Lin Huang
  • Patent number: 9711472
    Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hua Chang, Cheng-Lin Huang, Jing-Cheng Lin
  • Publication number: 20170186736
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.
    Type: Application
    Filed: March 14, 2017
    Publication date: June 29, 2017
    Inventors: Jui-Pin Hung, Cheng-Lin Huang, Hsien-Wen Liu, Shin-Puu Jeng
  • Patent number: 9691726
    Abstract: A method includes forming a first composite wafer including molding a plurality of device dies and a plurality of through-vias in a first molding material, and forming redistribution lines on opposite sides of the first molding material. The redistribution lines are inter-coupled through the plurality of through-vias. The method further includes forming a second composite wafer including stacking a plurality of dies to form a plurality of die stacks, and molding the plurality of die stacks in a second molding material. The second molding material fills gaps between the plurality of die stacks. The first composite wafer is bonded to the second composite wafer to form a third composite wafer.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Da Cheng, Hsien-Wei Chen, Cheng-Lin Huang, Meng-Tse Chen, Chung-Shi Liu
  • Publication number: 20170141059
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 18, 2017
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 9653423
    Abstract: An embodiment is an integrated circuit structure including a first die having a bump structure, and a second die having a pad structure. The first die is attached to the second die by bonding the bump structure and the pad structure. The bump structure includes a metal pillar, a metal cap layer on the metal pillar, a metal insertion layer on the metal cap layer, and a solder layer on the metal insertion layer. The pad structure includes at least one of a nickel (Ni) layer, a palladium (Pd) layer or a gold (Au) layer.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Cheng-Lin Huang
  • Publication number: 20170084571
    Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.
    Type: Application
    Filed: November 29, 2016
    Publication date: March 23, 2017
    Inventors: Cheng-Chieh Hsieh, Cheng-Lin Huang, Po-Hao Tsai, Shang-Yun Hou, Jing-Cheng Lin, Shin-Puu Jeng
  • Patent number: 9595510
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: March 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Cheng-Lin Huang, Hsien-Wen Liu, Shin-Puu Jeng
  • Patent number: 9511299
    Abstract: In a rotary dynamic simulation device and an audiovisual apparatus using the same, the rotary dynamic simulation device includes a fixed table (1), a motion mechanism (4), a carrying seat (3), and a rotation mechanism (4). The motion mechanism (2) having multiple degrees of freedom is disposed between the fixed table (1) and the carrying seat (3). The rotation mechanism (4) is disposed on the rack (5) to drive the fixed table (1) to rotate, so that the carrying seat (3) is rotatable between an entering position and a watch position of the rack (5).
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: December 6, 2016
    Assignee: BROGENT TECHNOLOGIES INC.
    Inventors: Deng-Horng Lai, Ke-Cheng Chien, Cheng-Lin Huang
  • Patent number: 9508666
    Abstract: A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Kuo-Ching Hsu, Cheng-Chieh Hsieh, Ying-Ching Shih, Po-Hao Tsai, Cheng-Lin Huang, Jing-Cheng Lin