Abstract: The present application provides a method of manufacturing a memory device. The method includes steps of providing a semiconductor substrate having an active area disposed over or in the semiconductor substrate, and a first isolation member extending into the semiconductor substrate and disposed adjacent to the active area; disposing an energy-decomposable mask over the semiconductor substrate and the first isolation member; irradiating a portion of the energy-decomposable mask with an electromagnetic radiation; removing the portion of the energy-decomposable mask irradiated with the electromagnetic radiation to form a patterned energy-decomposable mask; removing a portion of the semiconductor substrate exposed through the patterned energy-decomposable mask to form a trench; removing the patterned energy-decomposable mask; and forming a second isolation member within the trench.

Abstract: In a method of manufacturing a chip structure, a first carrier is attached on a back surface of a wafer, the wafer is diced into individual dies and there is a groove formed between the adjacent dies, then a second carrier is attached on an active surface of the wafer and the first carrier is removed to expose the groove, a back surface and a lateral surface of each of the dies, a heat dissipation cover is formed on the back surface and the lateral surface of each of the dies to obtain chip structures. The heat dissipation cover is provided to increase heat dissipation efficiency of the dies and prevent formation of metal debris which may contaminate the dies. Furthermore, the heat dissipation cover is prevented from being separated from the die.

Abstract: A gene chip includes a chip carrier, a plurality of DNA nanoballs assembled on the chip carrier, and a polymer film formed on the chip carrier and wrapping the DNA nanoballs. The polymer film includes at least one of a film of a positively charged polymer, a film of a positively charged polymer which is modified, a film of a zwitterionic polymer, and a composite polymer film. The composite polymer film is formed by a layer-by-layer self-assembly process of a positively charged polymer and a negatively charged polymer. The gene chip has good sequencing quality and different functions can be achieved by coating with different polymers, such as the chip surface rapidly drying out and surface non-specific adsorption. A method of preparing a gene chip is further disclosed.

Abstract: In semiconductor manufacturing, deionized (DI) water or another process fluid is flowed through a nonmetallic pipe and onto a semiconductor wafer. Static electric charge is discharged from the DI water or other process fluid flowing through the nonmetallic pipe via an electrically conductive material disposed on an outside of the nonmetallic pipe. The electrically conductive material disposed on the outside of the nonmetallic pipe is electrically grounded. The nonmetallic pipe may comprise fluoropolymer (PFA) based tubing. In some embodiments, the nonmetallic pipe includes: a PFA-NE pipe connected with a chamber or housing containing the wafer, and a second pipe connected with the PFA-NE pipe by a pipe connector, in which the second pipe is more electrically insulating than the PFA-NE pipe.

Abstract: An optical module is disclosed. The optical module includes a carrier and a lid disposed over the carrier. The carrier and the lid are collaboratively define a first cavity for accommodating a photonic component. The optical module also includes a first electrical contact disposed over a first side of the lid and configured to provide an electronic connection for the optical module. A first aperture penetrating the lid is formed at the first side of the lid and corresponds to a light transmission/reception area of the photonic component.

Abstract: This application provides a content recommendation method and apparatus, an electronic device, and a storage medium.

Abstract: The present application provides a method of manufacturing a memory device. The method includes steps of providing a semiconductor substrate having an active area disposed over or in the semiconductor substrate, and a first isolation member extending into the semiconductor substrate and disposed adjacent to the active area; disposing an energy-decomposable mask over the semiconductor substrate and the first isolation member; irradiating a portion of the energy-decomposable mask with an electromagnetic radiation; removing the portion of the energy-decomposable mask irradiated with the electromagnetic radiation to form a patterned energy-decomposable mask; removing a portion of the semiconductor substrate exposed through the patterned energy-decomposable mask to form a trench; removing the patterned energy-decomposable mask; and forming a second isolation member within the trench.

Abstract: The present application provides a method of manufacturing a memory device.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a fin, a gate structure positioned on the fin, impurity regions positioned on two sides of the fin, contacts positioned on the impurity regions, and conductive covering layers positioned on the contacts. The conductive covering layers are formed of copper germanide.

Abstract: An optical package structure and a method for manufacturing an optical package structure are provided. The optical package structure includes a sensor, an optical component and a fixing element. The optical component directly contacts the sensor. An interfacial area is defined by a contacting region of the optical component and the sensor. The fixing element is disposed outside of the interfacial area for bonding the optical component and the sensor.

Abstract: The present disclosure provides a semiconductor device structure with a conductive contact and a method for preparing the semiconductor device structure. The semiconductor device structure includes a dielectric layer disposed over a semiconductor substrate; a conductive contact penetrating through the dielectric layer; and a metal oxide layer separating the conductive contact from the dielectric layer, wherein the conductive contact and the metal oxide layer comprise a same metal.

Abstract: The present disclosure provides a semiconductor device structure with a conductive contact and a method for preparing the semiconductor device structure. The semiconductor device structure includes a dielectric layer disposed over a semiconductor substrate; a conductive contact penetrating through the dielectric layer; and a metal oxide layer separating the conductive contact from the dielectric layer, wherein the conductive contact and the metal oxide layer comprise a same metal.

Abstract: A semiconductor device package includes a substrate, a partition structure and a polymer film. The partition structure is disposed on the substrate and defines a space for accommodating a semiconductor device. The polymer film is adjacent to a side of the partition structure distal to the substrate. A first side surface of the polymer film substantially aligns with a first side surface of the partition structure.

Abstract: The present application discloses a semiconductor device with a programmable unit and a method for fabricating the semiconductor device. The semiconductor device includes a substrate comprising a first region and a second region; a first semiconductor element positioned in the first region of the substrate; a second semiconductor element positioned in the first region of the substrate and electrically coupled to the first semiconductor element; and a programmable unit positioned in the second region and electrically connected to the first semiconductor element.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a fin, a gate structure positioned on the fin, impurity regions positioned on two sides of the fin, contacts positioned on the impurity regions, and conductive covering layers positioned on the contacts. The conductive covering layers are formed of copper germanide.

Abstract: This application provides a content recommendation method and apparatus, an electronic device, and a storage medium.

Abstract: An optical package structure and a method for manufacturing an optical package structure are provided. The optical package structure includes a sensor, an optical component and a fixing element. The optical component directly contacts the sensor. An interfacial area is defined by a contacting region of the optical component and the sensor. The fixing element is disposed outside of the interfacial area for bonding the optical component and the sensor.

Abstract: A semiconductor package structure includes an organic substrate having a first surface, a first recess depressed from the first surface, a first chip over the first surface and covering the first recess, thereby defining a first cavity enclosed by a back surface of the first chip and the first recess, and a second chip over the first chip. The first cavity is an air cavity or a vacuum cavity.

Abstract: The present disclosure provides a semiconductor device with a graphene layer and a method for forming the same. The semiconductor device includes a first source/drain region and a second source/drain region disposed in a semiconductor substrate. The semiconductor device also includes a word line structure disposed in the semiconductor substrate and between the first source/drain region and the second source/drain region. The word line structure includes a gate dielectric layer, and a lower electrode layer disposed over the gate dielectric layer. The word line structure also includes an upper electrode layer disposed over the lower electrode layer, and a first graphene layer disposed between the lower electrode layer and the upper electrode layer.

Abstract: The present application discloses a semiconductor device with a programmable unit and a method for fabricating the semiconductor device. The semiconductor device includes a substrate comprising a first region and a second region; a first semiconductor element positioned in the first region of the substrate; a second semiconductor element positioned in the first region of the substrate and electrically coupled to the first semiconductor element; and a programmable unit positioned in the second region and electrically connected to the first semiconductor element.