Patents by Inventor Cheng Lu

Cheng Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12363979
    Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.
    Type: Grant
    Filed: May 10, 2024
    Date of Patent: July 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Kai Lin, Yung-Cheng Lu, Che-Hao Chang, Chi On Chui
  • Patent number: 12359104
    Abstract: This invention relates to a heat and humidity resistant adhesive composition, comprising a first part comprising at least one ethylenically unsaturated monomer; a second part comprising at least one initiator; and at least one blocked isocyanate compound comprised in the first part, the second part and/or a third separate part. The adhesive composition exhibits excellent aging performance under rigorous conditions.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: July 15, 2025
    Assignee: Henkel AG & Co. KGaA
    Inventors: Zhuming Shi, Cheng Lu, Jinqian Chen
  • Publication number: 20250227877
    Abstract: This disclosure is directed to a water-cooling plate having a first heat exchanging plate, a second heat exchanging plate and a main body. The first heat exchanging plate has a first fin structure. The second heat exchanging plate has a second fin structure. The main body has a partition plate, a first communication port and a second communication port, the main body has a first recess and a second recess, disposed at two sides of the partition plate. The partition plate has a communication opening communicated to the first recess and the second recess. The first fin structure is accommodated in the first recess to define a first channel, and the second fin structure is accommodated in the second recess to define a second channel. The first communication port, the first channel, the communication opening, the second channel, the second communication port are connected with each other sequentially.
    Type: Application
    Filed: October 11, 2024
    Publication date: July 10, 2025
    Inventors: Kuan-Cheng LU, Chih-Hao HSIA, Yu-Wei CHEN, Wei-Fang WU, Meng-Yu CHEN
  • Patent number: 12339543
    Abstract: An electronic device including a substrate, a signal line, and a spacer is provided. The signal line is disposed on the substrate and includes at least one curve segment. The spacer is disposed on the substrate and is disposed corresponding to the at least one curve segment.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: June 24, 2025
    Assignee: Innolux Corporation
    Inventors: You-Cheng Lu, Yung-Hsun Wu, Chia-Hao Tsai, Yi-Shiuan Cherng
  • Patent number: 12336211
    Abstract: A method of forming a semiconductor device includes forming a first layer on a semiconductor fin; forming a mask on the first layer, the mask being thicker on a top of the semiconductor fin than along a sidewall of the semiconductor fin. The first layer is thinned along the sidewall of the semiconductor fin using the mask. A second layer is formed on the semiconductor fin, the second layer covering the mask and the first layer. A dummy gate layer is formed on the semiconductor fin and patterned to expose a top surface of the semiconductor fin.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-I Lin, Ming-Ho Lin, Chun-Heng Chen, Yung-Cheng Lu
  • Publication number: 20250194202
    Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.
    Type: Application
    Filed: February 7, 2025
    Publication date: June 12, 2025
    Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu
  • Publication number: 20250186391
    Abstract: Disclosed are compounds of formula (I), and pharmaceutically acceptable salts thereof, which are inhibitors of the complement system. Also provided are pharmaceutical compositions comprising such a compound, and methods of using the compounds and compositions in the treatment or prevention of a disease or condition characterized by aberrant complement system activity.
    Type: Application
    Filed: October 9, 2020
    Publication date: June 12, 2025
    Inventors: Pravin L. Kotian, Yarlagadda S. Babu, Weihe Zhang, Peng-Cheng Lu, Andrew E. Spaulding, Wei Lv, Zhao Dang, Krishnan Raman
  • Patent number: 12322354
    Abstract: A display device includes a display panel. The display panel has a functional display area. The functional display area includes a plurality of display pixels and a plurality of light transmitting regions. The plurality of display pixels are around by the plurality of the light transmitting regions. A boundary between one of the plurality of display pixels and one of the plurality of light transmitting regions comprises an arc segment.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: June 3, 2025
    Assignee: Innolux Corporation
    Inventors: Chia-Hao Tsai, Ming-Jou Tai, Yi-Shiuan Cherng, Yu-Shih Tsou, You-Cheng Lu, Yung-Hsun Wu
  • Patent number: 12324170
    Abstract: A capacitor structure including a silicon material layer, a support frame layer, and a capacitor is provided. The support frame layer is disposed in the silicon material layer. The support frame layer has recesses. There is a cavity between two adjacent recesses. The support frame layer is located between the cavity and the recess. The support frame layer has a through hole directly above the cavity. The capacitor is disposed in the silicon material layer. The capacitor includes a first insulating layer and a first electrode layer. The first insulating layer is disposed on the support frame layer. The first electrode layer is disposed on the first insulating layer and fills the recess and the cavity.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: June 3, 2025
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Yu-Cheng Lu, Chia-Hao Yu, Yeh-Yu Chiang
  • Patent number: 12313946
    Abstract: An electronic device includes a substrate, a driving element, a first insulating layer, a pixel electrode layer, and a common electrode layer. The driving element is disposed on the substrate. The first insulating layer is disposed on the driving element. The pixel electrode layer is disposed on the first insulating layer. The first insulating layer comprises a hole, and the pixel electrode layer is electrically connected to the driving element through the hole. The common electrode layer is disposed on the pixel electrode layer. The common electrode layer comprises a slit, and the slit has an edge, and the edge is disposed in the hole.
    Type: Grant
    Filed: January 11, 2024
    Date of Patent: May 27, 2025
    Assignee: Innolux Corporation
    Inventors: Wei-Yen Chiu, Ming-Jou Tai, You-Cheng Lu, Yi-Shiuan Cherng, Yi-Hsiu Wu, Chia-Hao Tsai, Yung-Hsun Wu
  • Publication number: 20250158452
    Abstract: A wireless charging device includes a first substrate, at least one charging coil, a second substrate, a comb filter, at least one thermistor and a controller. The at least one charging coil is disposed on the first substrate. The second substrate is disposed above the at least one charging coil. The comb filter is disposed on the second substrate, and a projected area along a stacking direction at least partially overlaps the at least one charging coil. The at least one thermistor is disposed on the comb filter. The controller is connected to the at least one charging coil and connected to the at least one thermistor through a part of the comb filter.
    Type: Application
    Filed: February 29, 2024
    Publication date: May 15, 2025
    Applicants: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Guan-Jie JHAO, Ting Kai CHEN, Kuo Cheng LU, Kuo-Tong FANG
  • Patent number: 12294519
    Abstract: A first packet flow and a second packet flow support a first protocol, a third packet flow and a fourth packet flow support a second protocol, and a priority of the first protocol is lower than a priority of the second protocol. The first packet flow and the third packet flow are transmitted from a first ingress port to a first egress port. The second packet flow and the fourth packet flow are transmitted from a second ingress port to a second egress port. When the packet processing device is in a congested state, a bandwidth modulator performs a first suppression process on the first packet flow at the first ingress port, and the bandwidth modulator performs a second suppression process on the second packet flow at the second egress port or on the third packet flow at the first ingress port.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: May 6, 2025
    Assignee: Realtek Semiconductor Corporation
    Inventors: Kuo Cheng Lu, Chun-Ming Liu, Sheng Wen Lo
  • Patent number: 12293781
    Abstract: The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: May 6, 2025
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huai Lin, Guozhong Xing, Zuheng Wu, Long Liu, Di Wang, Cheng Lu, Peiwen Zhang, Changqing Xie, Ling Li, Ming Liu
  • Patent number: 12288814
    Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.
    Type: Grant
    Filed: January 24, 2024
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yi Kao, Hung Cheng Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Publication number: 20250131866
    Abstract: An electronic device including a plurality of pixels and a driving element is provided. Each of the plurality of pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The driving element drives each first sub-pixel of the plurality of pixels.
    Type: Application
    Filed: January 2, 2025
    Publication date: April 24, 2025
    Applicant: Innolux Corporation
    Inventors: Chia-Hao Tsai, You-Cheng Lu, Yi-Shiuan Cherng, Wei-Yen Chiu
  • Patent number: 12282369
    Abstract: The present application relates to a power-off protection method and apparatus, a device, and a storage medium. The main technical solution includes: in response to power sourcing equipment (PSE) being about to stop supplying power to a power device (PD) within a predetermined time, sending a first link layer discovery protocol (LLDP) message to the PD; receiving a second LLDP message, which is replied by the PD according to the first LLDP message; and powering off the PD according to the second LLDP message. The present application can not only avoid the interruption of the current tasks of a PD as much as possible, but can also record power-off reasons, so as to facilitate tracing to maintain the normal operation of a device, thereby ensuring the security of data and the device.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: April 22, 2025
    Assignee: Suzhou MetaBrain Intelligent Technology Co., Ltd.
    Inventors: Hung Hsin Chen, Bo Hsiung Chi, Yen Cheng Lu
  • Publication number: 20250126822
    Abstract: Semiconductor devices including fin-shaped isolation structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a fin extending from a semiconductor substrate; a shallow trench isolation (STI) region over the semiconductor substrate adjacent the fin; and a dielectric fin structure over the STI region, the dielectric fin structure extending in a direction parallel to the fin, the dielectric fin structure including a first liner layer in contact with the STI region; and a first fill material over the first liner layer, the first fill material including a seam disposed in a lower portion of the first fill material and separated from a top surface of the first fill material, a first carbon concentration in the lower portion of the first fill material being greater than a second carbon concentration in an upper portion of the first fill material.
    Type: Application
    Filed: December 27, 2024
    Publication date: April 17, 2025
    Inventors: Wan-Yi Kao, Fang-Yi Liao, Shu Ling Liao, Yen-Chun Huang, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Patent number: 12278252
    Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes a carrier conducting layer having a first surface; an absorption region is doped with a first dopant having a first conductivity type and a first peak doping concentration, wherein the carrier conducting layer is doped with a second dopant having a second conductivity type and a second peak doping concentration, wherein the carrier conducting layer comprises a material different from a material of the absorption region, wherein the carrier conducting layer is in contact with the absorption region to form at least one heterointerface, wherein a ratio between the first peak doping concentration of the absorption region and the second peak doping concentration of the carrier conducting layer is equal to or greater than 10; and a first electrode and a second electrode both formed over the first surface of the carrier conducting layer.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: April 15, 2025
    Assignee: Artilux, Inc.
    Inventors: Yen-Cheng Lu, Yun-Chung Na, Tsung-Ting Wu, Shu-Lu Chen, Chih-Wei Yeh
  • Publication number: 20250118569
    Abstract: A method includes following steps. A target layer is formed over a substrate. A first hard mask layer is formed over the target layer by a plasma generated using a first radio frequency generator and a second radio frequency generator. The first radio frequency generator and the second radio frequency generator have different powers. A second hard mask layer is formed over the first hard mask layer by a plasma generated using the first radio frequency generator without using the second radio frequency generator. A photoresist layer is formed over the second hard mask layer. The photoresist layer is exposed. The photoresist layer is developed. The first hard mask layer and the second hard mask layer are patterned using the photoresist layer as an etch mask. The target layer is patterned using the first hard mask layer and the second hard mask layer as an etch mask.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 10, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng LIU, Wei-Zhong CHEN, Chi-Ming YANG, Jr-Hung LI, Yung-Cheng LU
  • Patent number: 12266728
    Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.
    Type: Grant
    Filed: February 29, 2024
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yi Kao, Yu-Cheng Shiau, Chunyao Wang, Chih-Tang Peng, Yung-Cheng Lu, Chi On Chui