Abstract: Disclosed embodiments include a portable playback device performing functions comprising: (i) after receiving an indication to operate in a playback group while the first portable playback device is connected to a network device via a Personal Area Network (PAN) and not connected to a first Wireless Local Area Network (WLAN), establishing a second WLAN for the playback group; and (ii) after a second portable playback device has joined the second WLAN operated by the first portable playback device, streaming audio content received via the PAN connection from the first network device to the second portable playback device via the second WLAN operated by the first portable playback device, and playing the audio content in a groupwise manner with the second portable playback device. Other embodiments include portable playback devices performing similar functions via a peer-to-peer wireless link rather than the second WLAN.

Abstract: A deep neural network hardware accelerator comprises: an AXI-4 bus interface, an input cache area, an output cache area, a weighting cache area, a weighting index cache area, an encoding module, a configurable state controller module, and a PE array. The input cache area and the output cache area are designed as a line cache structure; an encoder encodes weightings according to an ordered quantization set, the quantization set storing the possible value of the absolute value of all of the weightings after quantization. During the calculation of the accelerator, the PE unit reads data from the input cache area and the weighting index cache area to perform shift calculation, and sends the calculation result to the output cache area. The accelerator uses shift operations to replace floating point multiplication operations, reducing the requirements for computing resources, storage resources, and communication bandwidth, and increasing the calculation efficiency of the accelerator.

Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region, second channel nanostructures in a second device region, a dielectric fin at a boundary between the first device region and the second device region, a high-k dielectric layer surrounding each of the first channel nanostructures and each of the second channel nanostructures and over the dielectric fin, a first work function layer surrounding each of the first channel nanostructures and over the high-k dielectric layer and a second work function layer surrounding each of the second channel nanostructures and over the high-k dielectric layer and the first work function layer. The first work function layer fully fills spaces between the first channel nanostructures and has an edge located above the dielectric fin. The second work function layer fully fills spaces between the second channel nanostructures.

Abstract: Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell along with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.

Abstract: A semiconductor device and method of making a conductive connector is provided. In an embodiment an opening is formed within a photoresist by adjusting the center point of an in-focus area during the exposure process. Once the photoresist has been developed to form an opening, an after development baking process is utilized to reshape the opening. Once reshaped, a conductive material is formed into the opening to take on the shape of the opening.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.

Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

Abstract: The proposed L-shaped field effect transistor comprises a horizontal FET and a vertical FET, wherein one end of the former is in contact with one end of the latter. Thus, the gates (or gate channels) of the two FETs can be separated by a distance so as to reduce mutual interference and simplify fabrication. When the two transistors are made of different materials, the contact area therebetween is small and the gates (or gate channels) of the two FETs are separated by a distance. Thus, the negative effect of interface defects close to the contact area can be reduced. To be compared to planar complementary FET (even FinFET and GAAFET), the proposed L-shaped FET can occupy a similar wafer area and have a similar overall thickness after subsequent metallization.

Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.

Abstract: Disclosed are compounds of formula I, II, III, and IV, and pharmaceutically acceptable salts thereof. The compounds are inhibitors of ALK2 kinase. Also provided are pharmaceutical compositions comprising a compound of formula I, II, III, or IV, or pharmaceutically acceptable salt thereof, and methods involving use of the compounds or pharmaceutically acceptable salts thereof and compositions in the treatment and prevention of various diseases and conditions, such as fibrodysplasia ossificans progressiva.

Abstract: A display device having a first region, a second region, and a third region set between the first region and the second region is provided. The display device includes a first sub-pixel, a second sub-pixel, and a first signal line. The first sub-pixel is arranged in the first region. The second sub-pixel is arranged in the second region, the area of the first sub-pixel is larger than the area of the second sub-pixel. The first signal line is arranged in the first region and the third region, and is electrically connected to the first sub-pixel and the second sub-pixel. At least a part of the first signal line extends in the first direction in the first region. At least another part of the first signal line extends in the second direction in the third region. The first direction is different from the second direction.

Abstract: Provided in the present invention is a multi-element co-doped sodium-ion positive electrode material, which is characterized in that the phase of the positive electrode material is an O3 phase, the space group thereof is R-3m, and the chemical formula thereof is Na?MaLibCucTidO2+?, wherein M is at least one of Ni, Co, Mn, Cr, V, Al, Fe, B, Si, Mg and Zn, 0.5???1, ?0.1???0.1, 0<a<0.95, 0<b<0.25, 0<c<0.3, 0<d<0.6, a+b+c+d=1, and the charge neutrality condition is met. Also provided in the present invention is a preparation method for and the use of the multi-element co-doped sodium-ion positive electrode material.

Abstract: A method includes forming a first fin structure and a second fin structure protruding from a substrate, forming a dielectric fin between the first fin structure and the second fin structure, recessing the dielectric fin to form a trench between the first fin structure and the second fin structure, and depositing a first dielectric layer on sidewall surfaces of the trench and on a top surface of the recessed dielectric fin. After the depositing the first dielectric layer, a second dielectric layer is deposited in the trench. The method further includes depositing a third dielectric layer to cap the second dielectric layer in the trench, and forming a gate structure on the first fin structure, the second fin structure, and the third dielectric layer.

Abstract: A device includes a semiconductor fin, an isolation layer, a dielectric fin structure, and a gate structure. The semiconductor fin is over a substrate. The isolation layer is over the substrate and adjacent the semiconductor fin. The dielectric fin structure is over the isolation layer and includes a bottom dielectric fin and a top dielectric fin. The isolation layer surrounds a bottom of the bottom dielectric fin. The top dielectric fin is over the bottom dielectric fin and is spaced apart from the isolation layer. The gate structure is across the semiconductor fin and the dielectric fin structure, wherein a portion of the gate structure in contact with the isolation layer has a first width, and another portion of the gate structure in contact with the top dielectric fin has a second width greater than the first width.

Abstract: A thin film transistor includes a first active layer, a second active layer, a first electrode, a second electrode and a third electrode. The first active layer includes a first surface away from a substrate. The second active layer includes a second surface in contact with the first surface. The first electrode, the first active layer and the second active layer have an overlapping region. The second electrode, the first active layer and the second active layer have an overlapping region. The third electrode, the first active layer and the second active layer have an overlapping region, and the third electrode is opposite to the second electrode. The second surface is located within the first surface, and a distance between at least part of a border of the second surface and a border of the first surface is less than or equal to 0.5 ?m.

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.

Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate structure formed over nanostructures. The gate structure includes a gate dielectric layer, and a fill layer over the gate dielectric layer. The semiconductor device structure includes a protection layer formed over the fill layer, and a gate spacer layer formed adjacent to the gate structure. The semiconductor device structure includes an insulating layer formed over the protection layer, and the insulating layer is in direct contact with the gate spacer layer.