Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a substrate having a first side and a second side. The substrate includes a pixel region. A photodetector is in the pixel region. A first doped region is in the pixel region. A second doped region is in the pixel region. The second doped region is vertically between the first doped region and the first side of the substrate. A doped well is in the substrate and laterally surrounds the pixel region. The doped well is partially in the second doped region. A portion of the second doped region is vertically between the doped well and the second side of the substrate. A trench isolation structure is in the semiconductor substrate and laterally surrounds the pixel region. A footprint of the trench isolation structure is within a footprint of the doped well.

Abstract: An electronic device may have a display with an array of inorganic light-emitting diodes. The array of inorganic light-emitting diodes may be overlapped by a polarizer layer such as a circular polarizer. Alternatively, the display may be a polarizer-free display without any polarizer layer over the array of inorganic light-emitting diodes. Each inorganic light-emitting diode may be surrounded by a diffuser that redirects edge-emissions towards a viewer. A top diffuser, a color filter layer, a microlens, and/or a microlens with color filtering and/or diffusive properties may also optionally overlap each inorganic light-emitting diode. The inorganic light-emitting diodes may have reflective sidewalls to mitigate edge-emissions. In this type of arrangement, the array of inorganic light-emitting diodes may be coplanar with one or more opaque masking layers. To mitigate reflections, the display may include two opaque masking layers having differing properties or a single phase separated opaque masking layer.

Abstract: An electronic device may have a display with an array of inorganic light-emitting diodes. The array of inorganic light-emitting diodes may be overlapped by a polarizer layer such as a circular polarizer. Alternatively, the display may be a polarizer-free display without any polarizer layer over the array of inorganic light-emitting diodes. Each inorganic light-emitting diode may be surrounded by a diffuser that redirects edge-emissions towards a viewer. A top diffuser, a color filter layer, a microlens, and/or a microlens with color filtering and/or diffusive properties may also optionally overlap each inorganic light-emitting diode. The inorganic light-emitting diodes may have reflective sidewalls to mitigate edge-emissions. In this type of arrangement, the array of inorganic light-emitting diodes may be coplanar with one or more opaque masking layers. To mitigate reflections, the display may include two opaque masking layers having differing properties or a single phase separated opaque masking layer.

Abstract: Provided is a cellulose composition, including a plurality of biocelluloses, wherein a diameter of the biocelluloses ranges from 20 to 30 nanometer, and a length of the biocelluloses ranges from 2000 to 3000 nanometer. The biocelluloses have good biocompatibility and can effectively enhance the efficiency of absorption and transmission of substances.

Abstract: A system for three-dimensional geometric guided student-teacher feature matching includes a multi-modal teacher model configured to determine feature matching between a pair of RGB-D images, each RGB-D image being a combination of a RGB image and its corresponding depth image; a mono-modal student model configured to determine feature matching from the pair of RGB images and the teacher model, the teacher model guiding the student model to learn RGB-induced depth information for the feature matching on both coarse and fine levels; a coarse-level knowledge transfer loss function for determining loss of transferring coarse-level matching knowledge from the teacher model to the student model; and a fine-level knowledge transfer loss function for determining loss of transferring fine-level matching knowledge from the teacher model to the student model, wherein the fine-level knowledge transfer loss function guides the student model to learn a fine-level prediction distribution with priority.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a gate structure, a source doped region, a drain doped region, source silicide patterns, and drain silicide patterns. The gate structure is disposed on the semiconductor substrate. The source doped region and the drain doped region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction, respectively. The source silicide patterns are disposed on the source doped region. The source silicide patterns are arranged in a second direction and separated from one another. The drain silicide patterns are disposed on the drain doped region. The drain silicide patterns are arranged in the second direction and separated from one another. The source silicide patterns and the drain silicide patterns are arranged misaligned with one another in the first direction.

Abstract: The present invention relates to variant Cas12i4 polypeptides, methods of producing the variant Cas12i4 polypeptides, processes for characterizing the variant Cas12i4 polypeptides, cells comprising the variant Cas12i4 polypeptides, and methods of using the variant Cas12i4 polypeptides. The invention further relates to complexes comprising a variant Cas12i4 polypeptide and an RNA guide, methods of producing the complexes, processes for characterizing the complexes, cells comprising the complexes, and methods of using the complexes.

Abstract: A memory device that includes a memory array and a pre-charge selecting circuit is introduced. The memory array includes a plurality of memory cells that are coupled to a plurality of bit lines and a plurality of word lines, wherein the plurality of word lines are configured to receive an input vector. The pre-charge selecting circuit is configured to selectively pre-charge a selected bit line according to a value of the input vector. The pre-charge selecting circuit is configured to determine whether the value of the input vector is less than a predefined threshold, and generate a gated pre-charge signal to skip pre-charging the selected bit line in response to determining that the value of the input vector is less than the predefined threshold.

Abstract: The present invention relates to variant polypeptides, methods of preparing the variant polypeptides, processes for characterizing the variant polypeptides, compositions and cells comprising the variant polypeptides, and methods of using the variant polypeptides. The invention further relates to complexes comprising the variant polypeptides, methods of producing the complexes, processes for characterizing the complexes, cells comprising the complexes, and methods of using the complexes.

Abstract: A photodetecting device is provided. The photodetecting device includes a silicon substrate, a germanium absorption region, and a plurality of microstructures. The silicon substrate includes a first surface and a second surface. The germanium absorption region is formed proximal to the first surface of the silicon substrate, and the germanium absorption region is configured to absorb photons and to generate photo-carriers. The plurality of microstructures are formed over the second surface of the silicon substrate, and the plurality of microstructures are configured to direct an optical signal towards the germanium absorption region. A system including an optical transmitter and an optical receiver is also provided.

Abstract: A method for measuring humidity at long range using simplified equipment includes creating a formula according to a relationship between multiple sets of known optical flow feature vectors and a known humidity. First and second images are obtained, wherein the first image and the second image are captured as being in the same range of capture. A plurality of feature points in the first image is obtained and an optical flow feature vector for each of the feature points according to apparent changes in position of each feature point according to the second image are calculated. The degree of current humidity according to the optical flow feature vectors and the formula is thus obtained.

Abstract: Disclosed are compounds of formula I, II, III, and IV, and pharmaceutically acceptable salts thereof. The compounds are inhibitors of ALK2 kinase. Also provided are pharmaceutical compositions comprising a compound of formula I, II, III, or IV, or pharmaceutically acceptable salt thereof, and methods involving use of the compounds or pharmaceutically acceptable salts thereof and compositions in the treatment and prevention of various diseases and conditions, such as fibrodysplasia ossificans progressiva.

Abstract: A method for a parallelism-aware wavelength-routed optical networks-on-chip design is proposed, which is executed by a computer, the method comprising using the computer to perform the following: providing a WRONoC netlist, design specs and design rules; performing a network construction such that potential positions of each core of a plurality of cores, a plurality of waveguides and a plurality of microring resonators (MRRs) are determined to create a topology; performing a message routing to minimize MRR type usage of the MRRs in the topology; and performing a MRR radius selection to select a radius from MRR-radius options for each MRR type in said topology based on a simulated annealing.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes a carrier conducting layer having a first surface; an absorption region is doped with a first dopant having a first conductivity type and a first peak doping concentration, wherein the carrier conducting layer is doped with a second dopant having a second conductivity type and a second peak doping concentration, wherein the carrier conducting layer comprises a material different from a material of the absorption region, wherein the carrier conducting layer is in contact with the absorption region to form at least one heterointerface, wherein a ratio between the first peak doping concentration of the absorption region and the second peak doping concentration of the carrier conducting layer is equal to or greater than 10; and a first electrode and a second electrode both formed over the first surface of the carrier conducting layer.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.

Abstract: A semiconductor image sensing structure includes a substrate having a first region and a second region, a metal grid in the first region, and a hybrid metal shield in the second region. The hybrid metal shield includes a first metallization layer, a second metallization layer disposed over the first metallization layer, a third metallization layer disposed over the second metallization layer, and a fourth metallization layer disposed over the third metallization layer. An included angle of the second metallization layer is between approximately 40° and approximately 60°.

Abstract: Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell along with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.

Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, where the first semiconductor fin and the second semiconductor fin extend upwards from a semiconductor substrate, depositing a second dielectric layer over the first dielectric layer, depositing a third dielectric layer over the second dielectric layer, where materials of the second dielectric layer and the third dielectric layer are different, and a material of the first dielectric layer is different from the material of the second dielectric layer and recessing the first dielectric layer and the second dielectric layer to expose sidewalls of the first semiconductor fin and the second semiconductor fin and to form a dummy fin between the first semiconductor fin and the second semiconductor fin.

Abstract: Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.