Abstract: A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl3)2CH2), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.

Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

Abstract: Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.

Abstract: A system for three-dimensional geometric guided student-teacher feature matching includes a multi-modal teacher model configured to determine feature matching between a pair of RGB-D images, each RGB-D image being a combination of a RGB image and its corresponding depth image; a mono-modal student model configured to determine feature matching from the pair of RGB images and the teacher model, the teacher model guiding the student model to learn RGB-induced depth information for the feature matching on both coarse and fine levels; a coarse-level knowledge transfer loss function for determining loss of transferring coarse-level matching knowledge from the teacher model to the student model; and a fine-level knowledge transfer loss function for determining loss of transferring fine-level matching knowledge from the teacher model to the student model, wherein the fine-level knowledge transfer loss function guides the student model to learn a fine-level prediction distribution with priority.

Abstract: An electronic device having a first region, a second region, and a third region set between the first region and the second region is provided. The electronic device includes a substrate, a first signal line disposed on the substrate, and a second signal line disposed on the substrate. The first signal line has two portions disposed in the third region and the two portions of the first signal line extends along two directions respectively. The second signal line has two portions disposed in the third region, the two portions of the second signal line extends along two directions respectively, and at least one of the first signal line and the second signal line is configured to transmit a gate signal. In the third region, the first signal line crosses the second signal line.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The device includes a dielectric layer, a ring waveguide embedded in the dielectric layer, and an input/output (I/O) waveguide embedded in the dielectric layer and optically coupled to the ring waveguide in a vertical manner. Materials of the dielectric layer, the ring waveguide, and the I/O waveguide are different.

Abstract: A photodetecting device is provided. The photodetecting device includes a silicon substrate, a germanium absorption region, and a plurality of microstructures. The silicon substrate includes a first surface and a second surface. The germanium absorption region is formed proximal to the first surface of the silicon substrate, and the germanium absorption region is configured to absorb photons and to generate photo-carriers. The plurality of microstructures are formed over the second surface of the silicon substrate, and the plurality of microstructures are configured to direct an optical signal towards the germanium absorption region. A system including an optical transmitter and an optical receiver is also provided.

Abstract: Aspects of online camera calibration for autonomous driving systems are described herein. The aspects may include a wheel odometer configured to measure a current speed of a moving vehicle, a speed monitor configured to determine that the current speed of the moving vehicle is high or low, and a camera calibrator configured to calibrate, while the vehicle is moving, at least one front camera of the moving vehicle according to a position of a vanishing point of two lane lines when the current speed is high. When the current speed is low and the vehicle is still moving, the camera calibrator may be further configured to calibrate multiple side and rear cameras of the moving vehicle according to a pose graph that includes relative poses of the multiple side and rear cameras.

Abstract: A fused ring acceptor material includes a structure of following formula (I).

Abstract: A coordinated fault-tolerant control method for a two-stage power module is provided. The two-stage power module includes a front-stage circuit and a rear-stage circuit. The front-stage circuit has a DC midpoint. Each of a first side circuit and a second side circuit of the rear-stage circuit includes two rear-stage switch sets. If one switch in one of the two rear-stage switch sets in the first side circuit fails, disable the other switch in the rear-stage switch set. Operate the other rear-stage switch set in the first side circuit normally. One of the two rear-stage switch sets in the second side circuit is operated normally, and the other of the two rear-stage switch sets in the second side circuit is disabled.

Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

Abstract: A semiconductor structure includes a plurality of semiconductor dies, a first stitch structure disposed in the plurality of semiconductor dies, and a second stitch structure disposed in at least two adjacent semiconductor dies of the plurality of semiconductor dies. The semiconductor dies are arranged to form a column or a row. The first stitch structure crosses all interfaces between the semiconductor dies. The second stitch structure crosses an interface between the at least two adjacent semiconductor dies.

Abstract: A semiconductor structure includes: a first electrical waveguide formed of a first dielectric material and configured to transmit an electrical signal; a second electrical waveguide formed of the first dielectric material and disposed adjacent to a first side of the first electrical waveguide; and a third electrical waveguide formed of the first dielectric material and disposed adjacent to a second side of the first electrical waveguide opposite the first side. The second electrical waveguide and the third electrical waveguide are configured to form a composite waveguide together with the first electrical waveguide for transmission of the electrical signal.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

Abstract: The present disclosure, in some embodiments, relates to a method of mitigating domain shift. The method includes accessing a first imaging data set having one or more first images from a first site and accessing a second imaging data set having one or more second images from a second site. The one or more first images respectively include a first on-target region. The one or more second images respectively include a second off-target region. The first on-target region is modified using the second off-target region to generate a calibrated first on-target region. The calibrated first on-target region has a first domain shift with respect to the second off-target region and the first on-target region has a second domain shift with respect to the first on-target region. The first domain shift is smaller than the second domain shift.

Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride layer is thicker than the first nitride layer.

Abstract: An exemplary package includes a photonic die, an electronic die, and a package component. The electronic die has an electronic device layer disposed between a frontside interconnect structure and a backside interconnect structure. The backside interconnect structure is configured to deliver power to the electronic device layer. The photonic die, the electronic die, and the package component are stacked top-to-bottom. The backside interconnect structure of the electronic die is connected to the package component, and the photonic die is connected to the electronic die. In some embodiments, the photonic die and the electronic die are each free of through semiconductor vias, such as through silicon vias. In some embodiments, a frontside interconnect structure of the photonic die is connected to the frontside interconnect structure of the electronic die. In some embodiments, a backside interconnect structure of the photonic die is connected to the frontside interconnect structure of the electronic die.

Abstract: Methods and compositions related to the engineering of a protein with L-cyst(e)ine degrading enzyme activity are described. For example, disclosed are modified cystathionine-?-lyases comprising one or more amino acid substitutions and capable of degrading L-cyst(e)ine. Furthermore, compositions and methods are provided for the treatment of cystinuria using the disclosed modified enzymes or nucleic acids encoding said enzymes.

Abstract: The technology described herein builds an optimal refresh schedule by minimizing a cost function constrained by an available refresh bandwidth. The cost function receives an importance score for a content item and a change rate for the content item as input in order to optimize the schedule. The cost function is considered optimized when a refresh schedule is found that minimizes the cost while using the available bandwidth and no more. The technology can build an optimized schedule to refresh content with incomplete change data, content with complete change data, or a mixture of content with and without complete change data. It can also re-learn content item change rates from its own schedule execution history and re-compute the refresh schedule, ensuring that this schedule takes into account the latest trends in content item updates.

Abstract: Soybean seeds with increased protein and having a modified expression or activity of at least one or two HECT E3 ligase polypeptides are provided. Methods for modifying expression or activity of HECT E3 ligase polypeptides and polynucleotides include genome editing to modify the transcription regulatory region or sequence encoding the HECT E3 ligase polypeptides and transformation with recombinant DNA constructs to enhance or suppress expression or activity of the HECT E3 ligase polypeptides. Plants containing the modifications produce seeds with altered composition such as one or more of increased protein, decreased soluble carbohydrate, increased oleic acid, decreased saturated fats such as palmitic and stearic acids, and decreased linoleic or linolenic acid.