Patents by Inventor Cheng-Ming Lin

Cheng-Ming Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11222892
    Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Shih-Chuan Chiu, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11211492
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1-x-yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01?x?0.1.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Carlos H. Diaz, Chun Hsiung Tsai, Yu-Ming Lin
  • Patent number: 11209736
    Abstract: A method for manufacturing a photomask is provided. The method includes: receiving a substrate having a hard mask disposed thereover; forming a patterned photoresist over the hard mask; patterning the hard mask using the patterned photoresist as a mask; and removing the patterned photoresist. The removing of the patterned photoresist includes: oxidizing organic materials over the substrate; applying an alkaline solution onto the patterned photoresist; and removing the patterned photoresist by mechanical impact. A method for cleaning a substrate and a photomask are also provided.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hsin Hsu, Hao-Ming Chang, Shao-Chi Wei, Sheng-Chang Hsu, Cheng-Ming Lin
  • Patent number: 11195938
    Abstract: A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a semiconductor fin, forming a source/drain structure on the semiconductor fin, forming an interfacial layer on the semiconductor fin, treating the interfacial layer with fluorine, forming a ferroelectric gate dielectric layer on the interfacial layer, treating the ferroelectric gate dielectric layer with fluorine, and forming a gate electrode layer on the ferroelectric gate dielectric layer.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: December 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Chi-On Chui, Ziwei Fang
  • Publication number: 20210349388
    Abstract: A method for manufacturing a semiconductor includes: receiving a photomask substrate including a shielding layer; defining a chip region and a peripheral region adjacent to the chip region; forming a design pattern in the chip region; forming a reference pattern by emitting one first radiation shot and a beta pattern by emitting a plurality of second radiation shots in the peripheral region, wherein a pixel size of the first radiation shot is greater than a pixel size of the second radiation shot; comparing a reference roughness of a boundary of the reference pattern and a beta roughness of a boundary of the beta pattern; transferring the design pattern to the shielding layer if a difference between the reference roughness and the beta roughness is within a tolerance; and transferring the design pattern of the photomask to a semiconductor substrate.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 11, 2021
    Inventors: CHENG-MING LIN, HAO-MING CHANG, CHIH-MING CHEN, CHUNG-YANG HUANG
  • Publication number: 20210351278
    Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer.
    Type: Application
    Filed: April 12, 2021
    Publication date: November 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ming LIN, Sai-Hooi Yeong, Ziwei Fang, Chi On Chui, Huang-Lin Chao
  • Publication number: 20210328064
    Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.
    Type: Application
    Filed: May 24, 2021
    Publication date: October 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming LIN, Sai-Hooi Yeong, Ziwei Fang, Chi On Chui, Huang-Lin Chao
  • Publication number: 20210328065
    Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.
    Type: Application
    Filed: June 29, 2021
    Publication date: October 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming LIN, Sai-Hooi YEONG, Ziwei FANG, Bo-Feng YOUNG, Chi On CHUI, Chih-Yu CHANG, Huang-Lin CHAO
  • Patent number: 11139397
    Abstract: The present disclosure relates to methods for forming a semiconductor device. The method includes forming a substrate and forming first and second spacers on the substrate. The method includes depositing first and second self-assembly (SAM) layers respectively on sidewalls of the first and second spacers and depositing a layer stack on the substrate and between and in contact with the first and second SAM layers. Depositing the layer stack includes depositing a ferroelectric layer and removing the first and second SAM layers. The method further includes depositing a metal compound layer on the ferroelectric layer. Portions of the metal compound layer are deposited between the ferroelectric layer and the first or second spacers. The method also includes depositing a gate electrode on the metal compound layer and between the first and second spacers.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Ziwei Fang, Chi On Chui, Huang-Lin Chao
  • Publication number: 20210296503
    Abstract: A semiconductor structure includes gate spacers disposed over a semiconductor layer, a hafnium-containing dielectric layer, where a first portion of the hafnium-containing dielectric layer having a first thickness is disposed over the semiconductor layer and a second portion of the hafnium-containing dielectric layer having a second thickness is disposed along sidewalls of the gate spacers, and where the first thickness is greater than the second thickness, and a metal gate electrode disposed over the hafnium-containing dielectric layer and between the gate spacers.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Chi On Chui, Ziwei Fang, Huang-Lin Chao
  • Publication number: 20210280960
    Abstract: An example of a device including a display panel and a border region around the display panel is provided. The device includes a cover disposed on the display panel and the border region. The cover is to protect the display panel and the border region. The device also includes an antenna with a keep out area disposed within a portion of the border region. The device includes a bezel disposed in the keep out area to support the cover. The bezel includes a partially filled portion to reduce a resonance shift of the antenna.
    Type: Application
    Filed: October 17, 2017
    Publication date: September 9, 2021
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Kuan-Jung HUNG, Cheng-Ming LIN
  • Publication number: 20210280679
    Abstract: A semiconductor device includes a substrate, a semiconductor fin extending from the substrate, a gate dielectric layer over the semiconductor fin, a metal nitride layer comprising a first portion over the gate dielectric layer and a second portion over the first portion, and a fill metal over the metal nitride layer. The second portion has an aluminum concentration greater than an aluminum concentration of the first portion.
    Type: Application
    Filed: May 21, 2021
    Publication date: September 9, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ming LIN, Peng-Soon LIM, Zi-Wei FANG
  • Publication number: 20210278760
    Abstract: In accordance with some embodiments of the present disclosure, an inspection method of a photomask includes performing a first inspection process, unloading the photomask from the inspection system, and performing a second inspection process. In the first inspection process, a common Z calibration map of an objective lens of an optical module with respect to the photomask is generated and stored, and a first image of the photomask is captured by using an image sensor while focusing the objective lens of the optical module based on the common Z calibration map. The photomask is unloaded from the inspection system. In the second inspection process, the photomask is loaded on the inspection system and a second image of the photomask is captured by using an image sensor while focusing an objective lens of an optical module based on the common Z calibration map generated in the first inspection process.
    Type: Application
    Filed: May 26, 2021
    Publication date: September 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsun-Cheng Tang, Cheng-Ming Lin, Sheng-Chang Hsu, Hao-Ming Chang, Way-Len Chang
  • Publication number: 20210255542
    Abstract: A method for forming a semiconductor device includes receiving a substrate having a first opening and a second opening formed thereon, wherein the first opening has a first width, and the second opening has a second width less than the first width; forming a protecting layer to cover the first opening and expose the second opening; performing a wet etching to widen the second opening with an etchant, wherein the second opening has a third width after the performing of the wet etching, and the third width of the second opening is substantially equal to the first width of the first opening; and performing a photolithography to transfer the first opening and the second opening to a target layer.
    Type: Application
    Filed: May 4, 2021
    Publication date: August 19, 2021
    Inventors: CHUNG-YANG HUANG, HAO-MING CHANG, MING CHE LI, YU-HSIN HSU, PO-CHENG LAI, KUAN-SHIEN LEE, WEI-HSIN LIN, YI-HSUAN LIN, WANG CHENG SHIH, CHENG-MING LIN
  • Patent number: 11079671
    Abstract: A method for fabricating a photomask is provided. The method includes several operations. A photomask substrate, having a chip region and a peripheral region adjacent to the chip region, is received. A reference pattern is formed by emitting one first radiation shot and a first beta pattern is formed by emitting a plurality of second radiation shots in the peripheral region. The plurality of second radiation shots are emitted along a first direction. A roughness of a boundary of the first beta pattern along the first direction is compared to a roughness of a boundary of the reference pattern along the first direction from a top view perspective. An alignment of the plurality of second radiation shots is adjusted if a result of the comparison exceeds a tolerance, or the photomask is formed. A photomask structure thereof and a method for manufacturing a semiconductor are also provided.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Ming Lin, Hao-Ming Chang, Chih-Ming Chen, Chung-Yang Huang
  • Patent number: 11069807
    Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Ziwei Fang, Bo-Feng Young, Chi On Chui, Chih-Yu Chang, Huang-Lin Chao
  • Publication number: 20210202287
    Abstract: The structure and methods of a reticle pod are provided. A reticle pod includes a base configured to support a reticle and a cover detachably coupled to the base. The cover includes a window that allows radiation at a wavelength between about 400 nm and about 700 nm to pass through with a transmittance of greater than 70%.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Inventors: WANG CHENG SHIH, HAO-MING CHANG, CHUNG-YANG HUANG, CHENG-MING LIN
  • Patent number: 11048163
    Abstract: In accordance with some embodiments of the present disclosure, an inspection method of a photomask includes performing a first inspection process, unloading the photomask from the inspection system, and performing a second inspection process. In the first inspection process, a common Z calibration map of an objective lens of an optical module with respect to the photomask is generated and stored, and a first image of the photomask is captured by using an image sensor while focusing the objective lens of the optical module based on the common Z calibration map. The photomask is unloaded from the inspection system. In the second inspection process, the photomask is loaded on the inspection system and a second image of the photomask is captured by using an image sensor while focusing an objective lens of an optical module based on the common Z calibration map generated in the first inspection process.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsun-Cheng Tang, Cheng-Ming Lin, Sheng-Chang Hsu, Hao-Ming Chang, Waylen Chang
  • Patent number: 11036129
    Abstract: A method for forming a photomask includes receiving a substrate having a first layer formed thereon, wherein a patterned second layer exposing portions of the first layer is disposed over the substrate, removing the exposed portions of the first layer through the patterned second layer to form a plurality of openings in the first layer, removing the patterned second layer, and performing a wet etching to remove portions of the first layer to widen the plurality of openings with an etchant. The etchant is in contact with a top surface of the first layer and sidewalls of the plurality of openings. Each of the plurality of openings has a first width prior to the performing of the wet etching and a second width after the performing of the wet etching. The second width is greater than the first width.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Yang Huang, Hao-Ming Chang, Ming Che Li, Yu-Hsin Hsu, Po-Cheng Lai, Kuan-Shien Lee, Wei-Hsin Lin, Yi-Hsuan Lin, Wang Cheng Shih, Cheng-Ming Lin
  • Patent number: 11031490
    Abstract: A method of forming a semiconductor device includes forming a sacrificial layer on sidewalls of gate spacers disposed over a semiconductor layer, forming a first hafnium-containing gate dielectric layer over the semiconductor layer in a first trench disposed between the gate spacers, removing the sacrificial layer to form a second trench between the gate spacers and the first hafnium-containing gate dielectric layer, forming a second hafnium-containing gate dielectric layer over the first hafnium-containing gate dielectric layer and on the sidewalls of the gate spacers, annealing the first and the second hafnium-containing gate dielectric layers while simultaneously applying an electric field, and subsequently forming a gate electrode over the annealed first and second hafnium-containing gate dielectric layers.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Chi On Chui, Ziwei Fang, Huang-Lin Chao