Abstract: A method includes forming a first semiconductor channel region and a second semiconductor channel region, wherein the second semiconductor channel region overlaps the first semiconductor channel region, forming a first gate dielectric on the first semiconductor channel region, and forming a second gate dielectric on the second semiconductor channel region. A first dipole film and a second dipole film are formed on the first gate dielectric and the second gate dielectric, respectively. The Dipole dopants in the first dipole film and the second dipole film are driven into the first gate dielectric and the second gate dielectric, respectively. The first dipole film and the second dipole film are then removed. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric to form first transistor and a second transistor, respectively.

Abstract: A thermoelectric cooler (TEC) is positioned to move heat away from a hot spot on a semiconductor chip and toward a dielectric substrate. This approach to thermal management is particularly effective when used in conjunction with a buried rail and back side power delivery. The TEC may be in a layer that contains solder connections be between two device layers an IC package. Alternatively, the TEC may be in a metal interconnect structure over the semiconductor substrate such as in a passivation stack at the top of the metal interconnect structure. TECs at either of these locations may be formed by wafer-level processing.

Abstract: A method includes forming a semiconductor fin; forming a gate dielectric layer over the semiconductor fin; depositing a first work function metal layer over the gate dielectric layer, the first work function metal layer having a first concentration of a work function material; depositing a second work function metal layer over the first work function metal layer, the second work function metal layer having a second concentration of the work function material, wherein the first concentration is higher than the second concentration; and forming a gate electrode over the second work function metal layer.

Abstract: A method for cleaning is provided. The method includes: removing a pellicle frame from a top surface of a photomask by debonding an adhesive between the photomask and the pellicle frame, wherein a first portion of the adhesive is remained on the top surface of the photomask, and removing the first portion of the adhesive on the top surface of the photomask, including applying an alkaline solution to the top surface of the photomask, and performing a mechanical impact to the photomask.

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

Abstract: In one example in accordance with the present disclosure, an example computing device is disclosed. The example computing device includes a housing. The example computing device also includes a rotatable antenna disposed within the housing. The rotatable antenna is to rotate such that a direction of radiation is maintained in a single direction as the housing is to rotate.

Abstract: A method includes: inspecting a reticle in a reticle pod, the reticle pod including a sealed space to accommodate the reticle, and the reticle pod further comprising a window arranged on an upper surface of the reticle pod, wherein the inspecting is performed through the window; and moving the reticle out of the reticle pod for performing a lithography operation using the reticle.

Abstract: The invention discloses a superconductor-metal conductive material, comprising a metal powder, a superconductor powder and an organic carrier adhesive, wherein the metal powder has 50-95 wt % of a total weight of said metal powder, said superconductor powder and said organic carrier binder, the superconductor powder has 4-40 wt % of said total weight, and the organic carrier binder has 1-10 wt % of said total weight, wherein the superconductor powder comprises one or more mixtures of La2-x-ySrxBayCuO4, La2-x-y BixSryCuO4, La2-x-y-z BixSryCaZCuO4, La2-x-y-z HgxBayCazCuO4, La2-x-ySrxTlyBazCuO6, La2-x-y-z-wSrxTlyBazCawCu2O8, and HgBa2Ca2Cu3O8, where each of x, y, z, and w is between 0.1 and 0.9.

Abstract: The present disclosure provides a method that includes providing a semiconductor structure having a bottom channel region and a top channel region over the bottom channel region; forming a gate dielectric layer over and wrapping around top channels in the top channel region; performing a radical treatment on the dielectric layer in a supercritical fluid; and forming a metal gate electrode on the dielectric layer.

Abstract: A method of forming a complementary field-effect transistor (CFET) device includes: forming a plurality of channel regions stacked vertically over a fin; forming an isolation structure between a first subset of the plurality of channel regions and a second subset of the plurality of channel regions; forming a gate dielectric material around the plurality of channel regions and the isolation structure; forming a work function material around the gate dielectric material; forming a silicon-containing passivation layer around the work function material; after forming the silicon-containing passivation layer, removing a first portion of the silicon-containing passivation layer disposed around the first subset of the plurality of channel regions and keeping a second portion of the silicon-containing passivation layer disposed around the second subset of the plurality of channel regions; and after removing the first portion of the silicon-containing passivation layer, forming a gate fill material around the plurali

Abstract: A semiconductor device includes a semiconductor feature, a low-k dielectric feature that is formed on the semiconductor feature, and a Si-containing layer that contains elements of silicon and that covers over the low-k dielectric feature. The Si-containing layer can prevent the low-k dielectric feature from being damaged in etch and/or annealing processes for manufacturing the semiconductor device.

Abstract: A device includes a gate structure, first and second gate spacers, source/drain regions, a refill metal structure, and a first dielectric liner. The gate structure is on a substrate. The first and second gate spacers are on opposite sides of the gate structure, respectively. The source/drain regions are spaced part from the gate structure at least in part by the first and second gate spacers. The refill metal structure is on the gate structure and between the first and second gate spacers. The first dielectric liner is atop the gate structure. The first dielectric liner interposes the refill metal structure and the first gate spacer.

Abstract: A method includes following steps. A semiconductor fin is formed extending from a substrate. A gate dielectric layer is formed to wrap around semiconductor fin. A P-type work function layer is formed to wrap around the gate dielectric layer. An N-type work function layer is formed to wrap around the P-type work function layer. The N-type work function layer has a work function different from a work function of the P-type work function layer. The N-type work function layer is treated such that an upper portion of the N-type work function layer has a different composition than a lower portion of the N-type work function layer.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of finFETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: The present disclosure describes a semiconductor device and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a source/drain (S/D) region on the fin structure not covered by the gate structure. The method further includes forming a contact structure on the S/D region. Forming the contact structure includes forming a transition metal chalcogenide (TMC) layer on the S/D region, and forming a contact plug on the TMC layer.

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

Abstract: A semiconductor device includes a semiconductor feature, a low-k dielectric feature that is formed on the semiconductor feature, and a Si-containing layer that contains elements of silicon and that covers over the low-k dielectric feature. The Si-containing layer can prevent the low-k dielectric feature from being damaged in etch and/or annealing processes for manufacturing the semiconductor device.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

Abstract: A device includes a semiconductor channel region and a gate structure. The semiconductor channel region is on a substrate. The gate structure is over the semiconductor channel region and comprises a gate dielectric layer, a first gate conductor layer, and a second gate conductor layer. The first gate conductor layer is over the gate dielectric layer. The first gate conductor layer includes oxygen. The second gate conductor layer is over the first gate conductor layer.