Patents by Inventor Cheng-Ming Lin

Cheng-Ming Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240266166
    Abstract: A low thermal budget dielectric material treatment is provided. An example method of the present disclosure includes providing a semiconductor structure, depositing a dielectric material over the semiconductor structure, treating the dielectric material with a gaseous species carried in a supercritical fluid, and after the treating, reducing a thickness of the dielectric material.
    Type: Application
    Filed: July 6, 2023
    Publication date: August 8, 2024
    Inventors: Cheng-Ming Lin, Szu-Hua Chen, Kenichi Sano, Wei-Yen Woon, Szuya Liao
  • Patent number: 12055850
    Abstract: A circuit layout patterning method includes: receiving a photomask substrate including a shielding layer; defining a chip region and a peripheral region adjacent to the chip region; forming a design pattern in the chip region; forming a reference pattern by emitting one first radiation shot and a beta pattern by emitting a plurality of second radiation shots in the peripheral region, wherein a pixel size of the first radiation shot is greater than a pixel size of the second radiation shot; comparing a width of the reference pattern and a width of the beta pattern; transferring the design pattern to the shielding layer if a difference between the width of the reference patterned and the width of the beta pattern is within a tolerance; and transferring the design pattern of the photomask to a semiconductor substrate.
    Type: Grant
    Filed: April 9, 2023
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Ming Lin, Hao-Ming Chang, Chih-Ming Chen, Chung-Yang Huang
  • Publication number: 20240258315
    Abstract: A dipole layer is formed over a semiconductor channel region. A doped gate dielectric layer is formed over the dipole layer. The doped gate dielectric layer contains an amorphous material. Via an annealing process, the amorphous material of the doped gate dielectric layer is converted into a material with at least partially crystal phases. After the doped gate dielectric layer is converted into the layer with partially crystal phases, a metal-containing gate electrode is formed over the doped gate dielectric layer.
    Type: Application
    Filed: June 16, 2023
    Publication date: August 1, 2024
    Inventors: Cheng-Ming Lin, Wei-Yen Woon, Szuya Liao
  • Publication number: 20240250086
    Abstract: Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives a p-dipole dopant from the p-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300° C. to about 500° C.). The p-dipole dopant can be titanium. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with a p-dipole dopant profile having a peak located at a high-k/interfacial interface ±0.5 nm.
    Type: Application
    Filed: May 11, 2023
    Publication date: July 25, 2024
    Inventors: Cheng-Ming LIN, Wei-Yen WOON, Szuya LIAO
  • Publication number: 20240249943
    Abstract: Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming an n-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives an n-dipole dopant from the n-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the n-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300° C. to about 500° C.). The n-dipole dopant is strontium, erbium, magnesium, or a combination thereof. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with an n-dipole dopant profile having a peak located at a high-k/interfacial interface ±0.5 nm.
    Type: Application
    Filed: May 10, 2023
    Publication date: July 25, 2024
    Inventors: Cheng-Ming LIN, Wei-Yen WOON, Szuya LIAO
  • Patent number: 12034058
    Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: July 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Ziwei Fang, Chi On Chui, Huang-Lin Chao
  • Publication number: 20240184195
    Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.
    Type: Application
    Filed: January 12, 2024
    Publication date: June 6, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh TIEN, Cheng-Hsuen CHIANG, Chih-Ming CHEN, Cheng-Ming LIN, Yen-Wei HUANG, Hao-Ming CHANG, Kuo-Chin LIN, Kuan-Shien LEE
  • Publication number: 20240186414
    Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.
    Type: Application
    Filed: January 2, 2024
    Publication date: June 6, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming LIN, Sai-Hooi YEONG, Ziwei FANG, Bo-Feng YOUNG, Chi On CHUI, Chih-Yu CHANG, Huang-Lin CHAO
  • Patent number: 11953448
    Abstract: A method for defect inspection includes receiving a substrate having a plurality of patterns; obtaining a gray scale image of the substrate, wherein the gray scale image includes a plurality of regions, and each of the regions has a gray scale value; comparing the gray scale value of each region to a gray scale references to define a first group, a second group and an Nth group, wherein each of the first group, the second group and the Nth group has at least a region; performing a calculation to obtain a score; and when the score is greater than a value, the substrate is determined to have an ESD defect, and when the score is less than the value, the substrate is determined to be free of the ESD defect.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsun-Cheng Tang, Hao-Ming Chang, Sheng-Chang Hsu, Cheng-Ming Lin
  • Patent number: 11906898
    Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Tien, Cheng-Hsuen Chiang, Chih-Ming Chen, Cheng-Ming Lin, Yen-Wei Huang, Hao-Ming Chang, Kuo-Chin Lin, Kuan-Shien Lee
  • Patent number: 11901450
    Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semicondutor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Ziwei Fang, Bo-Feng Young, Chi On Chui, Chih-Yu Chang, Huang-Lin Chao
  • Publication number: 20240047523
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The method includes forming a spacer over first sidewalls of the gate stack using a first precursor. The first precursor includes a first boron- and nitrogen-containing material having a first hexagonal ring structure, the spacer has a plurality of first layers, and each first layer includes boron and nitrogen.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Ming LIN, Szu-Hua CHEN, Wei-Yen WOON, Szuya LIAO
  • Publication number: 20240030281
    Abstract: A semiconductor device having a low-k isolation structure and a method for forming the same are provided. The semiconductor device includes channel structures, laterally extending on a substrate; gate structures, intersecting and covering the channel structures; and a channel isolation structure, laterally penetrating through at least one of the channel structures, and extending between separate sections of one of the gate structures along an extending direction of the one of the gate structures. A low-k dielectric material in the channel isolation structure comprises boron nitride.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Hua Chen, Cheng-Ming Lin, Han-Yu Lin, Wei-Yen Woon, Ming-Jie Huang, Ting-Gang Chen, Tai-Chun Huang, Ming-Chang Wen, Szuya Liao
  • Patent number: 11860530
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Patent number: 11855164
    Abstract: A semiconductor device includes a substrate, a semiconductor fin extending from the substrate, a gate dielectric layer over the semiconductor fin, a metal nitride layer comprising a first portion over the gate dielectric layer and a second portion over the first portion, and a fill layer over the metal nitride layer. The second portion has an aluminum concentration greater than an aluminum concentration of the first portion.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ming Lin, Peng-Soon Lim, Zi-Wei Fang
  • Publication number: 20230402528
    Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary method includes forming a dummy gate stack engaging a semiconductor fin over a substrate, conformally depositing a first dielectric layer over the substrate, conformally depositing a second dielectric layer over the first dielectric layer, etching back the first dielectric layer and the second dielectric layer to form a gate spacer extending along a sidewall surface of the dummy gate stack, the gate spacer comprising the first dielectric layer and the second dielectric layer, forming source/drain features in and over the semiconductor fin and adjacent the dummy gate stack, and replacing the dummy gate stack with a gate structure, where a dielectric constant of the first dielectric layer is less than a dielectric constant of silicon oxide, and the second dielectric layer is less easily to be oxidized than the first dielectric layer.
    Type: Application
    Filed: March 2, 2023
    Publication date: December 14, 2023
    Inventors: Szu-Hua Chen, Cheng-Ming Lin, Wei-Xiang You, Wei-De Ho, Wei-Yen Woon, Szuya Liao
  • Publication number: 20230367207
    Abstract: A method includes: inspecting a reticle in a reticle pod, the reticle pod including a sealed space to accommodate the reticle, and the reticle pod further comprising a window arranged on an upper surface of the reticle pod, wherein the inspecting is performed through the window; and moving the reticle out of the reticle pod for performing a lithography operation using the reticle.
    Type: Application
    Filed: July 30, 2023
    Publication date: November 16, 2023
    Inventors: WANG CHENG SHIH, HAO-MING CHANG, CHUNG-YANG HUANG, CHENG-MING LIN
  • Publication number: 20230367197
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Patent number: 11796909
    Abstract: A method of manufacturing a reticle includes: disposing the reticle in a reticle pod, the reticle pod forming a sealed space to accommodate the reticle, and the reticle pod comprising a window arranged on an upper surface of the reticle pod and configured to allow a radiation at a predetermined wavelength to pass through; and performing an inspection operation on the reticle through the window.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wang Cheng Shih, Hao-Ming Chang, Chung-Yang Huang, Cheng-Ming Lin
  • Publication number: 20230307828
    Abstract: In one example in accordance with the present disclosure, an example computing device is disclosed. The example computing device includes a housing. The example computing device also includes a rotatable antenna disposed within the housing. The rotatable antenna is to rotate such that a direction of radiation is maintained in a single direction as the housing is to rotate.
    Type: Application
    Filed: October 15, 2020
    Publication date: September 28, 2023
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: CHUN-CHIH LIU, CHENG-MING LIN, REN-HAO CHEN, CHIA HUNG KUO