Patents by Inventor Cheng-Ming Weng
Cheng-Ming Weng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953740Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.Type: GrantFiled: May 14, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 11947173Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: GrantFiled: May 5, 2023Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Publication number: 20240069277Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Kuo, Chen-Hua Yu, Cheng-Chieh Hsieh, Che-Hsiang Hsu, Chung-Ming Weng, Tsung-Yuan Yu
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Patent number: 11745662Abstract: An electrochromic mirror module including a light-transmissive substrate, an opaque touch sensing layer and an electrochromic device is provided. The light-transmissive substrate has a visible surface and a back surface disposed opposite to the visible surface. The opaque touch sensing layer and the electrochromic layer are disposed on the back surface. Distribution areas of the opaque touch sensing layer and the electrochromic layer are different on the back surface. An electrochromic mirror module including reflective layer and electrochromic device is also provided.Type: GrantFiled: August 20, 2020Date of Patent: September 5, 2023Assignee: Unimicron Technology Corp.Inventors: An-Sheng Lee, Meng-Chia Chan, Ming-Yuan Hsu, Po-Ching Chan, Shih-Yao Lin, Cheng-Ming Weng
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Publication number: 20210155161Abstract: An electrochromic mirror module including a light-transmissive substrate, an opaque touch sensing layer and an electrochromic device is provided. The light-transmissive substrate has a visible surface and a back surface disposed opposite to the visible surface. The opaque touch sensing layer and the electrochromic layer are disposed on the back surface. Distribution areas of the opaque touch sensing layer and the electrochromic layer are different on the back surface. An electrochromic mirror module including reflective layer and electrochromic device is also provided.Type: ApplicationFiled: August 20, 2020Publication date: May 27, 2021Inventors: An-Sheng LEE, Meng-Chia CHAN, Ming-Yuan HSU, Po-Ching CHAN, Shih-Yao LIN, Cheng-Ming WENG
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Patent number: 9320143Abstract: A wiring board includes a substrate, a first conductor layer, a second conductor layer, and a through-via conductor. The substrate has a first surface, a second surface, and at least one through-via. The first conductor layer is formed on the first surface, and the second conductor layer is formed on the second surface. The through-via conductor is formed in the through-via for electrically connecting to the first conductor layer and the second conductor layer. The through-via has a first depressed portion exposed in the first surface, a second depressed portion exposed in the second surface, and a tunnel portion between the first depressed portion and the second depressed portion for connecting the first depressed portion and the second depressed portion. The first depressed portion and the second depressed, portion are non-coaxial.Type: GrantFiled: March 18, 2013Date of Patent: April 19, 2016Assignee: Unimicron Technology Corp.Inventors: Cheng-Ming Weng, Wei-Ming Cheng, Han-Pei Huang
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Publication number: 20160012548Abstract: An exemplary embodiment of the present disclosure illustrates a method of automatically accounting. The method includes steps described as follows: a user device receives a plurality of purchase signals, and the user device operates an application to generate a user interface, wherein the user interface provides an account selection window according to the purchase signals received, and the account selection window provides a plurality of personal accounts for a user to select at least one personal account so as to view a plurality of purchase records of the at least one personal account selected.Type: ApplicationFiled: July 14, 2014Publication date: January 14, 2016Inventor: CHENG-MING WENG
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Publication number: 20140151107Abstract: A wiring board includes a substrate, a first conductor layer, a second conductor layer, and a through-via conductor. The substrate has a first surface, a second surface, and at least one through-via. The first conductor layer is formed on the first surface, and the second conductor layer is formed on the second surface. The through-via conductor is formed in the through-via for electrically connecting to the first conductor layer and the second conductor layer. The through-via has a first depressed portion exposed in the first surface, a second depressed portion exposed in the second surface, and a tunnel portion between the first depressed portion and the second depressed portion for connecting the first depressed portion and the second depressed portion. The first depressed portion and the second depressed, portion are non-coaxial.Type: ApplicationFiled: March 18, 2013Publication date: June 5, 2014Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: CHENG-MING WENG, WEI-MING CHENG, HAN-PEI HUANG
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Publication number: 20140151099Abstract: A laser drilling method of a wiring board is provided. In the method, a laser beam shines on a wiring substrate including an insulating layer to remove a portion of the insulating layer. The wiring substrate is placed in a focus section of the laser beam. The focus section contains a central region, an optical axis located in the central region, and a peripheral region surrounding the central region. The maximum light intensity of the focus section is located in the peripheral region.Type: ApplicationFiled: March 18, 2013Publication date: June 5, 2014Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: CHENG MING WENG, WEI-MING CHENG, HAN-PEI HUANG
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Patent number: 7687446Abstract: A method of removing the residue left after a plasma process is described. First, a substrate having at least a material layer thereon is provided. The material layer includes a metal. Then, a fluorine-containing plasma process is performed so that a residue containing the aforesaid metallic material is formed on the surface of the material layer. After that, a wet cleaning operation is performed using a cleaning agent to remove the residue. The cleaning agent is a solution containing water, a diluted hydrofluoric acid and an acid solution.Type: GrantFiled: February 6, 2006Date of Patent: March 30, 2010Assignee: United Microelectronics Corp.Inventors: Cheng-Ming Weng, Miao-Chun Lin, Mei-Chi Wang, Jiunn-Hsiung Liao, Wei-Cheng Yang
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Patent number: 7628866Abstract: A method of cleaning a wafer after an etching process is provided. A substrate having an etching stop layer, a dielectric layer, a patterned metal hard mask sequentially formed thereon is provided. Using the patterned metal hard mask, an opening is defined in the dielectric layer. The opening exposes a portion of the etching stop layer. A dry etching process is performed in the environment of helium to remove the etching stop layer exposed by the opening. A dry cleaning process is performed on the wafer surface using a mixture of nitrogen and hydrogen as the reactive gases. A wet cleaning process is performed on the wafer surface using a cleaning solution containing a trace amount of hydrofluoric acid.Type: GrantFiled: November 23, 2006Date of Patent: December 8, 2009Assignee: United Microelectronics Corp.Inventors: Miao-Chun Lin, Cheng-Ming Weng, Chun-Jen Huang
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Publication number: 20080121619Abstract: A method of cleaning a wafer after an etching process is provided. A substrate having an etching stop layer, a dielectric layer, a patterned metal hard mask sequentially formed thereon is provided. Using the patterned metal hard mask, an opening is defined in the dielectric layer. The opening exposes a portion of the etching stop layer. A dry etching process is performed in the environment of helium to remove the etching stop layer exposed by the opening. A dry cleaning process is performed on the wafer surface using a mixture of nitrogen and hydrogen as the reactive gases. A wet cleaning process is performed on the wafer surface using a cleaning solution containing a trace amount of hydrofluoric acid.Type: ApplicationFiled: November 23, 2006Publication date: May 29, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Miao-Chun Lin, Cheng-Ming Weng, Chun-Jen Huang
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Patent number: 7378343Abstract: A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.Type: GrantFiled: November 17, 2005Date of Patent: May 27, 2008Assignee: United Microelectronics Corp.Inventors: Jei-Ming Chen, Miao-Chun Lin, Kuo-Chih Lai, Mei-Ling Chen, Cheng-Ming Weng, Chun-Jen Huang, Yu-Tsung Lai
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Publication number: 20070249165Abstract: A dual damascene process is provided. A substrate having a conductive area is provided. An etching stop layer, a dielectric layer and a patterned hard mask layer are sequentially formed on the substrate. A first opening is formed in the dielectric layer exposed by the patterned hard mask layer. A first material layer having a high etching selectivity with respect to the dielectric layer is deposited to fill the first opening. A portion of the dielectric layer and the filling material layer are removed to form a trench and a second opening. The filling material layer exposed by the second opening is removed to expose part of the etching stop layer. A portion of the etching stop layer is removed to form a third opening. A conductive layer is formed in the trench and the third opening.Type: ApplicationFiled: April 5, 2006Publication date: October 25, 2007Inventors: Chun-Jen Huang, Cheng-Ming Weng, Meng-Jun Wang
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Publication number: 20070184996Abstract: A method of removing the residue left after a plasma process is described. First, a substrate having at least a material layer thereon is provided. The material layer includes a metal. Then, a fluorine-containing plasma process is performed so that a residue containing the aforesaid metallic material is formed on the surface of the material layer. After that, a wet cleaning operation is performed using a cleaning agent to remove the residue. The cleaning agent is a solution containing water, a diluted hydrofluoric acid and an acid solution.Type: ApplicationFiled: February 6, 2006Publication date: August 9, 2007Inventors: Cheng-Ming Weng, Miao-Chun Lin, Mei-Chi Wang, Jiunn-Hsiung Liao, Wei-Cheng Yang
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Publication number: 20070125750Abstract: A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues.Type: ApplicationFiled: February 14, 2007Publication date: June 7, 2007Inventors: Cheng-Ming Weng, Miao-Chun Lin, Chun-Jen Huang
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Publication number: 20070111514Abstract: A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.Type: ApplicationFiled: November 17, 2005Publication date: May 17, 2007Inventors: Jei-Ming Chen, Miao-Chun Lin, Kuo-Chih Lai, Mei-Ling Chen, Cheng-Ming Weng, Chun-Jen Huang, Yu-Tsung Lai
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Patent number: 7214612Abstract: A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal cross-section of the contact has an asymmetrically rounded outline. The conductive line is in the hard mask layer and the dielectric layer, and is located on and electrically connected to the contact. The conductive line has a laterally swelling portion on an edge portion of the first contact, wherein the borders of the laterally swelling portion and the edge portion are contiguous.Type: GrantFiled: August 31, 2005Date of Patent: May 8, 2007Assignee: United Microelectronics Corp.Inventors: Jen-Ren Huang, Cheng-Ming Weng, Miao-Chun Lin
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Publication number: 20070080386Abstract: A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal cross-section of the contact has an asymmetrically rounded outline. The conductive line is in the hard mask layer and the dielectric layer, and is located on and electrically connected to the contact. The conductive line has a laterally swelling portion on an edge portion of the first contact, wherein the borders of the laterally swelling portion and the edge portion are contiguous.Type: ApplicationFiled: December 8, 2006Publication date: April 12, 2007Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jen-Ren Huang, Cheng-Ming Weng, Miao-Chun Lin
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Patent number: 7192878Abstract: A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A first wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues. A second wet treatment is performed to completely remove the residues.Type: GrantFiled: May 9, 2005Date of Patent: March 20, 2007Assignee: United Microelectronics Corp.Inventors: Cheng-Ming Weng, Miao-Chun Lin, Chun-Jen Huang