Patents by Inventor Cheng Shih

Cheng Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-Layer Film Device and Method
    Publication number: 20180350993
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Application
    Filed: July 27, 2018
    Publication date: December 6, 2018
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • SEMICONDUCTOR DEVICE HAVING AN EXTRA LOW-K DIELECTRIC LAYER AND METHOD OF FORMING THE SAME
    Publication number: 20180308801
    Abstract: A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric material layers over a substrate. An adhesion layer is formed over the first IMD layer. An ELK dielectric layer is formed over the adhesion layer. A protection layer is formed over the ELK dielectric layer. A hard mask is formed over the protection layer and is patterned to create a window. Layers underneath the window are removed to create an opening. The removed layers include the protection layer, the ELK dielectric layer, the adhesion layer, and the first IMD layer. A metal layer is formed in the opening.
    Type: Application
    Filed: April 20, 2017
    Publication date: October 25, 2018
    Inventors: Po-Cheng SHIH, Chia Cheng CHOU, Li Chun TE
  • AIRWAY DEVICE
    Publication number: 20180264216
    Abstract: An airway device for a subject which has an airway tube having a distal end and a proximal end, and a laryngeal mask disposed surrounding the distal end of the airway tube, wherein the inner part of the laryngeal mask has a hollow body filled with a biocompatible thermosensitive hydrogel, wherein the biocompatible thermosensitive hydrogel is gelified within a temperature range such that the biocompatible thermosensitive hydrogel, upon being gelified, allows the laryngeal mask to fit over the circumference of a laryngeal inlet of the subject.
    Type: Application
    Filed: December 22, 2017
    Publication date: September 20, 2018
    Applicant: E-PROSPERITY & DEVELOPMENT CO., Ltd.
    Inventors: Cheng-Shih Lien, Tsu-Tai Lin, Ming-Thau Sheu, Chen-Chun Liao
  • Method and Apparatus for Increasing Luminous Intensity of an Ultraviolet Light Emitting Diode
    Publication number: 20180227997
    Abstract: A method for increasing the luminous intensity of an ultraviolet light emitting diode includes heating an ultraviolet light emitting diode to a working temperature, and supplying electricity to the ultraviolet light emitting diode at the working temperature to make the ultraviolet light emitting diode emit ultraviolet light. An apparatus for increasing the luminous intensity of an ultraviolet light emitting diode includes a substrate, an ultraviolet light emitting diode mounted on the substrate, an electric heater mounted on the substrate, a temperature sensor, and a controller electrically connected to the ultraviolet light emitting diode, the electric heater, and the temperature sensor. The controller can heat the ultraviolet light emitting diode through the substrate.
    Type: Application
    Filed: May 17, 2017
    Publication date: August 9, 2018
    Inventors: Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Chih-Cheng Shih, Bo-Wei Chen, Chung-I Yang
  • Method and apparatus for increasing luminous intensity of an ultraviolet light emitting diode
    Patent number: 10045414
    Abstract: A method for increasing the luminous intensity of an ultraviolet light emitting diode includes heating an ultraviolet light emitting diode to a working temperature, and supplying electricity to the ultraviolet light emitting diode at the working temperature to make the ultraviolet light emitting diode emit ultraviolet light. An apparatus for increasing the luminous intensity of an ultraviolet light emitting diode includes a substrate, an ultraviolet light emitting diode mounted on the substrate, an electric heater mounted on the substrate, a temperature sensor, and a controller electrically connected to the ultraviolet light emitting diode, the electric heater, and the temperature sensor. The controller can heat the ultraviolet light emitting diode through the substrate.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: August 7, 2018
    Assignee: National Sun Yat-Sen University
    Inventors: Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Chih-Cheng Shih, Bo-Wei Chen, Chung-I Yang
  • Full-frame adhesive anti-fog film structure
    Patent number: 10042185
    Abstract: The present invention is to provide a full-frame adhesive anti-fog film structure, comprising: an anti-fog film, which has a front side and a back side opposing the front side; and an adhesive, which is disposed at an edge of the back side and arranged along the edge so as to be frame-shaped. The anti-fog film of the present invention is attachable to a planar, cylindrical or spherical lens through the full frame-shaped adhesive so that not only can the anti-fog film be fully attached to the lens but the full attachment of film also prevents bubbles from forming between the two attached surfaces. Also, an airtight space is formed between the full-frame adhesive anti-fog film structure and the lens to stop heat transfer and prevent fog from being formed, so as to not only provide good vision to users but also reduce the chance that the user will fall prey to an accident if the user's view is blocked.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: August 7, 2018
    Assignee: U-GIN ADVANCED MATERIAL CO., LTD.
    Inventor: Cheng-Shih Wang
  • METHOD FOR PROCESSING ELECTRONIC COMPONENTS BY A SUPERCRITICAL FLUID
    Publication number: 20180195200
    Abstract: A method for processing an electronic component using a supercritical fluid includes introducing the supercritical fluid into a cavity. The supercritical fluid is doped with a hydrogen isotope-labeled compound, an organic metal compound, an element selecting from a halogen element, oxygen, sulfur, selenium, phosphorus or arsenic, or a compound containing the element. An electronic component in the cavity is modified by the supercritical fluid at a temperature above a critical temperature of the supercritical fluid and a pressure above a critical pressure of the supercritical fluid.
    Type: Application
    Filed: September 22, 2017
    Publication date: July 12, 2018
    Inventors: TING-CHANG CHANG, KUAN-CHANG CHANG, CHIH-CHENG SHIH, CHIH-HUNG PAN
  • METHOD FOR PROCESSING A BIOMEDICAL MATERIAL BY A SUPERCRITICAL FLUID
    Publication number: 20180193525
    Abstract: A method for processing a biomedical material using a supercritical fluid includes introducing the supercritical fluid into a cavity. The supercritical fluid is doped with a hydrogen isotope-labeled compound, an organic metal compound, an element selecting from a halogen element, oxygen, sulfur, selenium, phosphorus or arsenic, or a compound containing the element. The biomedical material in the cavity is modified by the supercritical fluid at a temperature above a critical temperature of the supercritical fluid and a pressure above a critical pressure of the supercritical fluid.
    Type: Application
    Filed: November 21, 2017
    Publication date: July 12, 2018
    Inventors: Ting-Chang Chang, Kuan-Chang Chang, Chih-Cheng Shih, Chih-Hung Pan, Chih-Yang Lin
  • WIRELESS EXPANDING SYSTEM AND WIRELESS EXPANDING METHOD
    Publication number: 20180129468
    Abstract: A wireless expanding system includes an electronic device and a wireless expanding interface, and the wireless expanding interface is connected to the electronic device. The electronic device is configured to execute an operational procedure, and to generate an operational signal according to the operational procedure. The wireless expanding interface is configured to transmit the operational signal to a function expanding device. The function expanding device includes a displayer. When the displayer receives the operational signal via the wireless expanding interface, the displayer is configured to display an operational interface of the operational procedure.
    Type: Application
    Filed: April 4, 2017
    Publication date: May 10, 2018
    Inventors: Feng-Ku WANG, Lung-Hsun SONG, Chun-Chi LIN, Chia-Cheng SHIH
  • Methods for Reducing Dual Damascene Distortion
    Publication number: 20180102319
    Abstract: An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer.
    Type: Application
    Filed: December 4, 2017
    Publication date: April 12, 2018
    Inventors: Chao-Chun Wang, Chung-Chi Ko, Po-Cheng Shih
  • Multi-Layer Film Device and Method
    Publication number: 20180040732
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Application
    Filed: August 2, 2016
    Publication date: February 8, 2018
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • LOW-K DIELECTRIC INTERCONNECT SYSTEMS
    Publication number: 20180005882
    Abstract: A method of fabricating a semiconductor device includes forming a low-k dielectric layer over a substrate and depositing a cap layer over the low-k dielectric layer. A treatment process is performed to the cap layer. After the treatment process to the cap layer is performed, the low-k dielectric layer is etched to form a plurality of trenches using the cap layer as an etching mask.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 4, 2018
    Inventors: Po-Cheng SHIH, Chia Cheng CHOU, Chung-Chi KO
  • Interconnect Structure and Method
    Publication number: 20170372948
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Application
    Filed: August 25, 2017
    Publication date: December 28, 2017
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo, Po-Cheng Shih, Tze-Liang Lee, Jun-Yi Ruan
  • Methods for reducing dual damascene distortion
    Patent number: 9842804
    Abstract: An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Chun Wang, Chung-Chi Ko, Po-Cheng Shih
  • Reaction Method with Homogeneous-Phase Supercritical Fluid and Apparatus for Homogeneous-Phase Supercritical Fluid Reaction
    Publication number: 20170341050
    Abstract: The present disclosure provides a reaction method with homogeneous-phase supercritical fluid, including: preparing a supercritical fluid and a solute; supplying the supercritical fluid and the solute into a molecular sieve component to uniformly mix the supercritical fluid and the solute in the molecular sieve component, forming a homogeneous-phase supercritical fluid; and supplying the homogeneous-phase supercritical fluid into a reaction chamber for conducting a reaction.
    Type: Application
    Filed: October 12, 2016
    Publication date: November 30, 2017
    Inventors: Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Chih-Cheng Shih, Chih-Hung Pan
  • Resistive Random Access Memory
    Publication number: 20170317281
    Abstract: A resistive random access memory overcomes the low durability of the conventional resistive random access memory. The resistive random access memory includes a first electrode, a second electrode, an enclosing layer and an oxygen-containing resistance changing layer. The first and second electrodes are separate from each other. The enclosing layer forms a first via-hole. The oxygen-containing resistance changing layer is arranged for the first via-hole. The first and second electrodes and the enclosing layer jointly enclose the oxygen-containing resistance changing layer. Each of the first electrode, the second electrode and the enclosing layer is made of an element not containing oxygen.
    Type: Application
    Filed: July 19, 2016
    Publication date: November 2, 2017
    Inventors: Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Chih-Cheng Shih, Chih-Hung Pan
  • Low-k dielectric interconnect systems
    Patent number: 9768061
    Abstract: A method of fabricating a semiconductor device includes forming a low-k dielectric layer over a substrate and depositing a cap layer over the low-k dielectric layer. A treatment process is performed to the cap layer. After the treatment process to the cap layer is performed, the low-k dielectric layer is etched to form a plurality of trenches using the cap layer as an etching mask.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Cheng Shih, Chia Cheng Chou, Chung-Chi Ko
  • INTERCONNECT STRUCTURE AND METHOD
    Publication number: 20170256445
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Application
    Filed: March 2, 2016
    Publication date: September 7, 2017
    Inventors: Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo, Po-Cheng Shih, Tze-Liang Lee, Jun-Yi Ruan
  • Interconnect structure and method
    Patent number: 9754822
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo, Po-Cheng Shih, Tze-Liang Lee, Jun-Yi Ruan
  • Method of making interconnect structure
    Patent number: 9748134
    Abstract: A method of making a semiconductor device including forming a first adhesion layer over a substrate. The method further includes forming a second adhesion layer over the first adhesion layer, where the second adhesion layer is formed using an inert gas with a first flow rate under a first RF power. Additionally, the method includes forming a low-k dielectric layer over the second adhesion layer, where the low-k dielectric layer is formed using the inert gas with a second flow rate under a second RF power under at least one of the following two conditions: 1) the second flow rate is different from the first flow rate; or 2) the second RF power is different from the first RF power. Furthermore, the method includes forming an opening in the dielectric layer, the second adhesion layer, and the first adhesion layer. Additionally, the method includes forming a conductor in the opening.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Cheng Shih, Yu-Yun Peng, Chia Cheng Chou, Joung-Wei Liou