Abstract: A method for forming a magnetoresistive (MR) sensor element. There is first provided a substrate. There is then formed over the substrate a seed layer. There is then formed contacting a pair of opposite ends of the seed layer a pair of patterned conductor lead layer structures. There is then etched, while employing an ion etch method, the seed layer and the pair of patterned conductor lead layer structures to form an ion etched seed layer and a pair of ion etched patterned conductor lead layer structures. Finally, there is then formed upon the ion etched seed layer and the pair of ion etched patterned conductor lead layers structures a magnetoresistive (MR) layered structure. Within the magnetoresistive (MR) sensor element, the pair of patterned conductor lead layer structures may be formed within a pair of recesses within an ion etch recessed dielectric isolation layer.

Abstract: A method for forming a longitudinally magnetically biased dual stripe magnetoresistive (DSMR) sensor element comprises forming a first patterned magnetoresistive (MR) layer. Contact the opposite ends of the patterned magnetoresistive (MR) layer with a first pair of stacks defining a track width of the first magnetoresistive (MR) layer, each of the stacks including a first Anti-Ferro-Magnetic (AFM) layer and a first lead layer. Then anneal the device in the presence of a longitudinal external magnetic field. Next, form a second patterned magnetoresistive (MR) layer above the previous structure. Contact the opposite ends of the second patterned magnetoresistive (MR) layer with a second pair of stacks defining a second track width of the second patterned magnetoresistive (MR) layer. Each of the second pair of stacks includes spacer layer composed of a metal, a Ferro-Magnetic (FM) layer, a second Anti-Ferro-Magnetic (AFM) layer and a second lead layer.

Abstract: A method for making a magnetic head slider having a protective coating on the rails thereof, the protective coating containing a thin adhesion layer, a thin layer of amorphous hydrogenated carbon, and a thin masking layer. The protective coating is deposited on the air bearing surface of the slider after the thin film magnetic heads are lapped to a chosen dimension, but before the pattern of rails is produced on the air bearing surface. The protective coating protects the magnetic head during the rail fabrication process and in usage in a magnetic recording system protects the magnetic head from wear and corrosion damage.

Abstract: A sputtering apparatus for coating a substrate comprising a first electrode for supporting a target material and a second electrode for supporting a substrate, upon which the coating is deposited. A source of RF power is connected to impose an RF voltage across the electrodes to produce a glow discharge in the space between the electrodes, and shutter means is provided in the space between the electrodes. The shutter means has means for blocking a substantial part of the sputtered atoms from the target electrode glow discharge traveling at or near normal incidence and at least one opening shaped to permit a substantial part of the sputtered atoms from the target electrode traveling at an oblique angle to impinge upon the substrate to produce a thin film coating of the target material.

Abstract: A magnetic head slider having a protective coating on the rails thereof, the protective coating comprising a thin adhesion layer, a thin layer of amorphous hydrogenated carbon, and a thin masking layer. The protective coating is deposited on the air bearing surface of the slider after the thin film magnetic heads are lapped to a chosen dimension, but before the pattern of rails is produced on the air bearing surface. The protective coating protects the magnetic head during the rail fabrication process and in usage in a magnetic recording system protects the magnetic head from wear and corrosion damage.

Abstract: A magnetic head slider having a protective coating on the rails thereof, the protective coating comprising a thin adhesion layer and a thin layer of amorphous hydrogenated carbon. The protective coating is deposited on the air bearing surface of the slider after the thin film magnetic heads are lapped to a chosen dimension, but before the pattern of rails is produced on the air bearing surface. The protective coating protects the magnetic head during the rail fabrication process and in usage in a magnetic recording system protects the magnetic head from wear and corrosion damage.

Abstract: The method for making a shielded magnetoresistive (MR) sensor in which the first shield is made of sendust and the second shield is made of permalloy. The method comprises the stages of depositing a layer of sendust to form a first shield; heat treating the sendust layer at a temperature greater than 400.degree. C.; depositing a first electrically insulating layer; depositing, in the presence of a magnetic field, a MR layer; depositing a second layer of electrically insulating material; and, depositing a layer of permalloy to form the second shield.

Abstract: Disclosed is a self-aligned process for providing an improved bipolar transistor structure.The process includes the chemically etching of an intermediate insulating layer to undercut another top layer of a different insulating material in a self-aligned emitter process wherein the spacing of the emitter contact to the polysilicon base contact is reduced to a magnitude of approximately 0.2 to 0.3 micrometers. In addition, in the process an emitter plug is formed to block the emitter region from the heavy P+ ion dose implant of the extrinsic base.

Abstract: A method of forming a wide deep dielectric filled isolation trench in the surface of a silicon semiconductor substrate by forming a wide plug of chemical vapor deposited silicon dioxide in the trench, filling the remaining unfilled trench portions by chemical vapor depositing a layer of silicon dioxide over the substrate and etching back this layer. The method produces chemically pure, planar wide deep dielectric filled isolation trenches and may also be used to simultaneously produce narrow deep dielectric filled isolation trenches.

Abstract: Disclosed is a process for forming an improved bipolar transistor in a silicon substrate of a first conductivity type, said silicon substrate having a planar surface, a subcollector region of a second conductivity type formed in said substrate, an epitaxial layer of said second conductivity type formed on said planar surface of said substrate, and first, second and third spaced apart recessed oxide isolation regions extending from the planar surface of said epitaxial layer into said substrate, a subcollector reach-through region positioned between said second and third recessed oxide isolation regions, said subcollector reach-through region extending from said planar surface of said epitaxial layer to said subcollector region, said process including the following steps: deposit, using chemical vapor deposition techniques, a layer of doped polysilicon on the exposed surface of said substrate said dopant being of said first conductivity type; deposit, using chemical vapor deposition techniques a first layer of

Abstract: Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.

Abstract: Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.

Abstract: An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layers containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction.

Abstract: A method for device fabrication utilizing a self-aligned process. A combination of advanced semiconductor processing techniques including Deep Dielectric Isolation by reactive-ion etching, etching and refilling, planarizing with oxides and resists, and differential thermal oxidation are used to form devices having small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls which extend from the epitaxial silicon surface through the N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3 .mu.m. A shallow oxide trench extends from the epitaxial silicon surface to the upper portion of the N+ subcollector and separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter.

Abstract: Disclosed is a self-aligned process for providing an improved high-performance bipolar transistor. The transistor device region is isolated from the other devices on the wafer by a wide deep oxide trench. The deep oxide trench which has nearly vertical sidewalls, extends from the epitaxial silicon surface through the N.sup.+ subcollector region into the P.sup.- substrate. A shallow oxide trench is used to separate the collector reach through region from the base region. A heavily doped polysilicon layer is used to dope and make contact to the transistor base as well as define the emitter window through which the emitter is doped. In the structure, the separation between the emitter contact and the polysilicon base contact is reduced to a very small value. This is achieved by employing the self-aligned process in accordance with the invention. Metal contact to the polysilicon base contact is done over the deep trench oxide isolation.

Abstract: Disclosed is a self-aligned process for providing an improved bipolar transistor structure.The process includes the chemically etching of an intermediate insulating layer to undercut another top layer of a different insulating material in a self-aligned emitter process wherein the spacing of the emitter contact to the polysilicon base contact is reduced to a magnitude of approximately 0.2 to 0.3 micrometers. In addition, in the process an emitter plug is formed to block the emitter region from the heavy P+ ion dose implant of the extrinsic base.

Abstract: A method for device fabrication disclosed is a self-aligned process. The device formed has small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls. The deep trench extends from the epitaxial silicon surface through N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3.0 .mu.m. A shallow oxide trench extending from the epitaxial silicon surface to the upper portion of the N+ subcollector separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in low collector-base capacitance which is a very important parameter in ultra-high performance integrated circuit devices.

Abstract: A bipolar transistor isolated by deep recessed oxide 19, with shallow recessed oxide 15 separating the base 32, 37 from collector contact 35, with polysilicon contact 26 to base extrinsic region 37, the polysilicon being self-aligned with the emitter 36 and the emitter contact.

Abstract: A bipolar transistor structure formed in a monolithic silicon semiconductor substrate of p type having a planar surface comprising: a subcollector of n type formed in the substrate; an epitaxial layer of n type formed on said planar surface of said substrate and also having a planar surface, the epitaxial layer having a thickness in the order of 1.0 to 1.

Abstract: An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layer containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction.