Patents by Inventor Cheng-Ta Ko

Cheng-Ta Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11516910
    Abstract: A circuit board structure includes a redistribution structure layer, a build-up circuit structure layer, and a connection structure layer. The redistribution structure layer has a first and second surface, and includes an inner and outer dielectric layer, first connecting pads, and chip pads. A bottom surface of each first connecting pad is aligned with the first surface, and the chip pads are protruded from and located on the second surface. The build-up circuit structure layer includes second connecting pads. The connection structure layer is disposed between the redistribution structure layer and the build-up circuit structure layer and includes a substrate and conductive paste pillars penetrating the substrate. The first connecting pads are electrically connected to the second connecting pads via the conductive paste pillars, respectively. A top surface of each conductive paste pillar is aligned with the first surface of the redistribution structure layer.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: November 29, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Chia-Yu Peng, John Hon-Shing Lau, Kai-Ming Yang, Pu-Ju Lin, Cheng-Ta Ko, Tzyy-Jang Tseng
  • Publication number: 20220375919
    Abstract: A method of manufacturing package structure with following steps is disclosed herein. An insulating composite layer is formed on a metal layer of a carrier board. A chip packaging module including a sealant and a first chip embedded therein is disposed on the insulating composite layer, in which the first chip has a plurality of conductive pads. A first circuit layer module including a dielectric layer and a circuit layer is formed on the chip packaging module, in which the circuit layer is on the dielectric layer and electrically connected to the conductive pads through a conductive vias in the dielectric layer. A second chip is disposed on the first circuit layer module. A second circuit layer module is formed on the first circuit layer module and the second chip. A protecting layer is formed on the second circuit layer module.
    Type: Application
    Filed: August 8, 2022
    Publication date: November 24, 2022
    Inventors: Kai-Ming YANG, Chen-Hao LIN, Cheng-Ta KO, John Hon-Shing LAU, Yu-Hua CHEN, Tzyy-Jang TSENG
  • Publication number: 20220367307
    Abstract: A manufacturing method of a chip package structure includes the following steps. A plurality of chips is disposed on a first insulating layer. The back surface of each of the chips is in direct contact with the first insulating layer. A stress buffer layer is formed to extend and cover the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips. The stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening. A plurality of solder balls is electrically connected to the redistribution layer exposed by the blind holes. A singularizing process is performed to form a plurality of chip package structures separated from each other.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Pu-Ju Lin, Kai-Ming Yang, Cheng-Ta Ko
  • Publication number: 20220344248
    Abstract: A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.
    Type: Application
    Filed: April 21, 2021
    Publication date: October 27, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Cheng-Ta Ko, Pu-Ju Lin, Kai-Ming Yang, Chi-Hai Kuo, Chia-Yu Peng, Tzyy-Jang Tseng
  • Publication number: 20220336333
    Abstract: A package structure includes at least one first redistribution layer, at least one second redistribution layer, a chip pad, a solder ball pad, a chip, a solder ball, and a molding compound. The first redistribution layer includes a first dielectric layer and a first redistribution circuit that fills a first opening and a second opening of the first dielectric layer. The first dielectric layer is aligned with the first redistribution circuit. The second redistribution layer includes a second and a third dielectric layers and a second redistribution circuit. The third dielectric layer is aligned with the second redistribution circuit. The chip pad and the solder ball pad are electrically connected to the first and the second redistribution circuits respectively. The chip and the solder ball are disposed on the chip pad and the solder ball pad respectively. The molding compound at least covers the chip and the chip pad.
    Type: Application
    Filed: April 19, 2021
    Publication date: October 20, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Cheng-Ta Ko, Pu-Ju Lin, Kai-Ming Yang, Chia-Yu Peng, Chi-Hai Kuo, Tzyy-Jang Tseng
  • Patent number: 11476234
    Abstract: A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit layer have been formed on the carrier. A flat structure layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and covers the flat structure layer and a portion of the first dielectric layer. A second patterned circuit layer is formed on the second dielectric layer. The second patterned circuit layer includes a plurality of pads. An orthographic projection of the flat structure layer on the carrier overlaps orthographic projections of the pads on the carrier. A plurality of chips are disposed on the pads. A molding compound is formed to cover the second dielectric layer and encapsulate the chips and the pads.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: October 18, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Pu-Ju Lin, Chi-Hai Kuo, Kai-Ming Yang, Cheng-Ta Ko
  • Publication number: 20220328387
    Abstract: A package carrier includes a first redistribution layer having a first upper surface and a first lower surface and including a plurality of first redistribution circuits, a plurality of conductive through holes, a plurality of photoimageable dielectric layers, and a plurality of chip pads and a second redistribution layer disposed on the first upper surface of the first redistribution layer. The second redistribution layer has a second upper surface and a second lower surface aligned with and directly connected to the first upper surface of the first redistribution layer and includes a plurality of second redistribution circuits, a plurality of conductive structures, a plurality of Ajinomoto build-up Film (ABF) layers, and a plurality of solder ball pads. A line width and a line pitch of each of the first redistribution circuits are smaller than a line width and a line pitch of each of the second redistribution circuits.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 13, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Cheng-Ta Ko, Pu-Ju Lin, Kai-Ming Yang, Chi-Hai Kuo, Chia-Yu Peng, Tzyy-Jang Tseng
  • Patent number: 11462452
    Abstract: A chip package structure including a chip, a stress buffer layer, a first insulating layer, a redistribution layer, a second insulating layer, and a solder ball is provided. The chip has an active surface, a back surface and a peripheral surface. The stress buffer layer covers the active surface and the peripheral surface, and the first insulating layer is disposed on the back surface. A bottom surface of the stress buffer layer is aligned with the back surface of the chip. The redistribution layer is electrically connected to the chip through an opening of the stress buffer layer. The second insulating layer covers the stress buffer layer and the redistribution layer. The solder ball is disposed in a blind hole of the second insulating layer and electrically connected to the redistribution layer. A top surface of the solder ball protrudes from an upper surface of the second insulating layer.
    Type: Grant
    Filed: January 24, 2021
    Date of Patent: October 4, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Pu-Ju Lin, Kai-Ming Yang, Cheng-Ta Ko
  • Patent number: 11460255
    Abstract: A vapor chamber device and a manufacturing method are disclosed. The vapor chamber has a housing and multiple independent chambers. The housing includes two shells opposite to each other. The independent chambers are formed between the two shells. Each independent chamber contains a working fluid and has at least one diversion bump and a capillary structure. The diversion bump is formed on an inner surface of the second shell, and the capillary structure is mounted on the diversion bump. When the vapor chamber device is vertically mounted to a heat source, the independent chambers at an upper portion of the vapor chamber device still contain the working fluid. The working fluid in the independent chambers may not all flow to a bottom of the vapor chamber device. Therefore, a contact area between the working fluid and the heat source is increased and heat dissipation efficiency is improved.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: October 4, 2022
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Pu-Ju Lin, Ying-Chu Chen, Wei-Ci Ye, Chi-Hai Kuo, Cheng-Ta Ko
  • Patent number: 11445617
    Abstract: A package structure is disclosed herein. The package structure includes an insulating composite layer, a sealant disposed on the insulating composite layer, a first chip embedded in the sealant and having a plurality of first conductive pads exposed through the sealant, a circuit layer module having a plurality of circuit layers and a plurality of dielectric layers having a plurality of conductive vias, a second chip embedded in the circuit layer module and has a plurality of second conductive pads electrically connected to the circuit layers through the conductive vias, and a protecting layer having a plurality of openings disposed on the circuit layer module, in which the openings expose a portion of the circuit layer module.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: September 13, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Kai-Ming Yang, Chen-Hao Lin, Cheng-Ta Ko, John Hon-Shing Lau, Yu-Hua Chen, Tzyy-Jang Tseng
  • Publication number: 20220271208
    Abstract: A light emitting diode (LED) package structure includes a glass substrate, conductive through holes, active elements, an insulating layer, LEDs and pads. The glass substrate has an upper surface and a lower surface. The conductive through holes penetrate the glass substrate and connect the upper and the lower surfaces. The active elements are disposed on the upper surface of the glass substrate and electrically connected to the conductive through holes. The insulating layer is disposed on the upper surface and covers the active elements. The LEDs are disposed on the insulating layer and electrically connected to at least one of the active elements. The pads are disposed on the lower surface of the glass substrate and electrically connected to the conductive through holes. A source of at least one active elements is directly electrically connected to at least one of the corresponding pads through the corresponding conductive through hole.
    Type: Application
    Filed: April 12, 2021
    Publication date: August 25, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Jeng-Ting Li, Chi-Hai Kuo, Cheng-Ta Ko, Pu-Ju Lin
  • Patent number: 11424216
    Abstract: A fabrication method of an electronic device bonding structure includes the following steps. A first electronic component including a first conductive bonding portion is provided. A second electronic component including a second conductive bonding portion is provided. A first organic polymer layer is formed on the first conductive bonding portion. A second organic polymer layer is formed on the second conductive bonding portion. Bonding is performed on the first electronic component and the second electronic component through the first conductive bonding portion and the second conductive bonding portion, such that the first electronic component and the second electronic component are electrically connected. The first organic polymer layer and the second organic polymer layer diffuse into the first conductive bonding portion and the second conductive bonding portion after the bonding. An electronic device bonding structure is also provided.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: August 23, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Chia-Fu Hsu, Kai-Ming Yang, Pu-Ju Lin, Cheng-Ta Ko
  • Publication number: 20220256717
    Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.
    Type: Application
    Filed: April 20, 2021
    Publication date: August 11, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Cheng-Ta Ko, Pu-Ju Lin, Chi-Hai Kuo, Kai-Ming Yang, Chia-Yu Peng, Shao-Chien Lee, Tzyy-Jang Tseng
  • Patent number: 11410933
    Abstract: A package structure, including a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips, is provided. The bridge includes a silicon substrate, a redistribution layer, and multiple bridge pads. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The bridge is embedded in the intermediate layer. The bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: August 9, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Cheng-Ta Ko, Pu-Ju Lin, Tzyy-Jang Tseng, Ra-Min Tain, Kai-Ming Yang
  • Patent number: 11410971
    Abstract: A chip package structure includes a substrate, a first chip, a second chip, a bridge, a plurality of first bumps, a plurality of second bumps, a plurality of third bumps and a plurality of solder balls. A first active surface of the first chip and a second active surface of the second chip face a first surface of the substrate. The bridge includes a high-molecular polymer layer and a pad layer located on the high-molecular polymer layer. The first chip is electrically connected to the substrate through the first bumps. The second chip is electrically connected to the substrate through the second bumps. The first chip and the second chip are electrically connected to the pad layer through the third bumps. The first bumps and the second bumps have the same size. The solder balls are disposed on a second surface of the substrate and electrically connected to the substrate.
    Type: Grant
    Filed: November 15, 2020
    Date of Patent: August 9, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Pu-Ju Lin, Cheng-Ta Ko, Ra-Min Tain
  • Patent number: 11410940
    Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: August 9, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Pu-Ju Lin, Cheng-Ta Ko, Yu-Hua Chen, Tzyy-Jang Tseng, Ra-Min Tain
  • Patent number: 11408730
    Abstract: A stress measuring device and a stress measuring method for measuring a stress distribution of an object are provided. The stress measuring method includes: receiving a first-dimension image of the object; marking an area of the first-dimension image to generate a marked area; calculating a first stress applied to the marked area and transforming the marked area to a strained marked area corresponding to a second-dimension image to generate a determination result; and calculating the stress distribution corresponding to the first-dimension image of the object according to the determination result.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: August 9, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: I-Hung Chiang, Hung-Hsien Ko, Cheng-Ta Pan, Wen-Yung Yeh, Cheng-Chung Lee
  • Publication number: 20220246810
    Abstract: A manufacturing method of a package structure is provided, which includes the following steps. A carrier having a surface is provided. A copper foil layer is laminated on the surface of the carrier. A subtractive process is performed on the copper foil layer to form a copper foil circuit layer on the carrier. The copper foil circuit layer exposes a part of the surface of the carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the carrier. A first surface of the copper foil circuit layer is aligned with a second surface of the build-up structure layer. At least one electronic component is disposed on the build-up structure layer. A package colloid is formed to cover the electronic component and the build-up structure layer. The carrier is removed to expose the first surface of the copper foil circuit layer.
    Type: Application
    Filed: March 22, 2021
    Publication date: August 4, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Cheng-Ta Ko, Pu-Ju Lin, Chi-Hai Kuo, Kai-Ming Yang
  • Publication number: 20220208630
    Abstract: A chip packaging structure includes a chip, a redistribution layer, a solder ball, an encapsulant, and a stress buffer layer. The chip has an active surface and a back surface opposite to each other, and a peripheral surface connected to the active surface and the back surface. The redistribution layer is disposed on the active surface of the chip. The solder ball is disposed on the redistribution layer, and the chip is electrically connected to the solder ball through the redistribution layer. The encapsulant encapsulates the active surface and the back surface of the chip, the redistribution layer, and part of the solder ball. The stress buffer layer at least covers the peripheral surface of the chip. An outer surface of the stress buffer layer is aligned with a side surface of the encapsulant.
    Type: Application
    Filed: January 22, 2021
    Publication date: June 30, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Kai-Ming Yang, Chia-Yu Peng, Pei-Chi Chen, Pu-Ju Lin, Cheng-Ta Ko
  • Publication number: 20220208631
    Abstract: A chip package structure including a chip, a stress buffer layer, a first insulating layer, a redistribution layer, a second insulating layer, and a solder ball is provided. The chip has an active surface, a back surface and a peripheral surface. The stress buffer layer covers the active surface and the peripheral surface, and the first insulating layer is disposed on the back surface. A bottom surface of the stress buffer layer is aligned with the back surface of the chip. The redistribution layer is electrically connected to the chip through an opening of the stress buffer layer. The second insulating layer covers the stress buffer layer and the redistribution layer. The solder ball is disposed in a blind hole of the second insulating layer and electrically connected to the redistribution layer. A top surface of the solder ball protrudes from an upper surface of the second insulating layer.
    Type: Application
    Filed: January 24, 2021
    Publication date: June 30, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Pu-Ju Lin, Kai-Ming Yang, Cheng-Ta Ko