Patents by Inventor Cheng-Ta Ko
Cheng-Ta Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220256717Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.Type: ApplicationFiled: April 20, 2021Publication date: August 11, 2022Applicant: Unimicron Technology Corp.Inventors: John Hon-Shing Lau, Cheng-Ta Ko, Pu-Ju Lin, Chi-Hai Kuo, Kai-Ming Yang, Chia-Yu Peng, Shao-Chien Lee, Tzyy-Jang Tseng
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Patent number: 11410940Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.Type: GrantFiled: February 8, 2021Date of Patent: August 9, 2022Assignee: Unimicron Technology Corp.Inventors: Pu-Ju Lin, Cheng-Ta Ko, Yu-Hua Chen, Tzyy-Jang Tseng, Ra-Min Tain
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Patent number: 11410971Abstract: A chip package structure includes a substrate, a first chip, a second chip, a bridge, a plurality of first bumps, a plurality of second bumps, a plurality of third bumps and a plurality of solder balls. A first active surface of the first chip and a second active surface of the second chip face a first surface of the substrate. The bridge includes a high-molecular polymer layer and a pad layer located on the high-molecular polymer layer. The first chip is electrically connected to the substrate through the first bumps. The second chip is electrically connected to the substrate through the second bumps. The first chip and the second chip are electrically connected to the pad layer through the third bumps. The first bumps and the second bumps have the same size. The solder balls are disposed on a second surface of the substrate and electrically connected to the substrate.Type: GrantFiled: November 15, 2020Date of Patent: August 9, 2022Assignee: Unimicron Technology Corp.Inventors: Tzyy-Jang Tseng, Pu-Ju Lin, Cheng-Ta Ko, Ra-Min Tain
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Patent number: 11410933Abstract: A package structure, including a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips, is provided. The bridge includes a silicon substrate, a redistribution layer, and multiple bridge pads. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The bridge is embedded in the intermediate layer. The bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.Type: GrantFiled: May 7, 2021Date of Patent: August 9, 2022Assignee: Unimicron Technology Corp.Inventors: John Hon-Shing Lau, Cheng-Ta Ko, Pu-Ju Lin, Tzyy-Jang Tseng, Ra-Min Tain, Kai-Ming Yang
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Publication number: 20220246810Abstract: A manufacturing method of a package structure is provided, which includes the following steps. A carrier having a surface is provided. A copper foil layer is laminated on the surface of the carrier. A subtractive process is performed on the copper foil layer to form a copper foil circuit layer on the carrier. The copper foil circuit layer exposes a part of the surface of the carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the carrier. A first surface of the copper foil circuit layer is aligned with a second surface of the build-up structure layer. At least one electronic component is disposed on the build-up structure layer. A package colloid is formed to cover the electronic component and the build-up structure layer. The carrier is removed to expose the first surface of the copper foil circuit layer.Type: ApplicationFiled: March 22, 2021Publication date: August 4, 2022Applicant: Unimicron Technology Corp.Inventors: Tzyy-Jang Tseng, Cheng-Ta Ko, Pu-Ju Lin, Chi-Hai Kuo, Kai-Ming Yang
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Publication number: 20220208630Abstract: A chip packaging structure includes a chip, a redistribution layer, a solder ball, an encapsulant, and a stress buffer layer. The chip has an active surface and a back surface opposite to each other, and a peripheral surface connected to the active surface and the back surface. The redistribution layer is disposed on the active surface of the chip. The solder ball is disposed on the redistribution layer, and the chip is electrically connected to the solder ball through the redistribution layer. The encapsulant encapsulates the active surface and the back surface of the chip, the redistribution layer, and part of the solder ball. The stress buffer layer at least covers the peripheral surface of the chip. An outer surface of the stress buffer layer is aligned with a side surface of the encapsulant.Type: ApplicationFiled: January 22, 2021Publication date: June 30, 2022Applicant: Unimicron Technology Corp.Inventors: Kai-Ming Yang, Chia-Yu Peng, Pei-Chi Chen, Pu-Ju Lin, Cheng-Ta Ko
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Publication number: 20220208631Abstract: A chip package structure including a chip, a stress buffer layer, a first insulating layer, a redistribution layer, a second insulating layer, and a solder ball is provided. The chip has an active surface, a back surface and a peripheral surface. The stress buffer layer covers the active surface and the peripheral surface, and the first insulating layer is disposed on the back surface. A bottom surface of the stress buffer layer is aligned with the back surface of the chip. The redistribution layer is electrically connected to the chip through an opening of the stress buffer layer. The second insulating layer covers the stress buffer layer and the redistribution layer. The solder ball is disposed in a blind hole of the second insulating layer and electrically connected to the redistribution layer. A top surface of the solder ball protrudes from an upper surface of the second insulating layer.Type: ApplicationFiled: January 24, 2021Publication date: June 30, 2022Applicant: Unimicron Technology Corp.Inventors: Pu-Ju Lin, Kai-Ming Yang, Cheng-Ta Ko
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Patent number: 11366381Abstract: A mask structure and a manufacturing method of the mask structure are provided. The mask structure includes a transparent substrate, a patterned metal layer, and a plurality of microlens structures. The patterned metal layer is disposed on the transparent substrate and exposing a portion of the transparent substrate. The microlens structures are disposed on the transparent substrate exposed by a portion of the patterned metal layer and being in contact with the portion of the patterned metal layer.Type: GrantFiled: April 26, 2019Date of Patent: June 21, 2022Assignee: Unimicron Technology Corp.Inventors: Pu-Ju Lin, Shih-Lian Cheng, Yu-Hua Chen, Cheng-Ta Ko, Jui-Jung Chien, Wei-Tse Ho
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Patent number: 11362057Abstract: A chip package structure includes a substrate, at least two chips, a plurality of first pads, a plurality of first micro bumps, and a bridging element. The substrate has a first surface and a second surface opposite to the first surface. The two chips are disposed on the first surface of the substrate and are horizontally adjacent to each other. Each chip has an active surface. The first pads are disposed on the active surface of each of the chips. The first micro bumps are disposed on the first pads and have the same size. The bridging element is disposed on the first micro bumps such that one of the chips is electrically connected to another of the chips through the first pads, the first micro bumps, and the bridging element.Type: GrantFiled: November 18, 2019Date of Patent: June 14, 2022Assignee: Unimicron Technology Corp.Inventors: Pu-Ju Lin, Cheng-Ta Ko, Ra-Min Tain, Tzyy-Jang Tseng
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Publication number: 20220146207Abstract: A vapor chamber device has a housing and multiple chambers. The housing includes two shells opposite to each other. The chambers are formed between the two shells. Each chamber contains a working fluid and has at least one diversion bump and a capillary structure. The diversion bump is formed on an inner surface of the second shell, and the capillary structure is mounted on the diversion bump. Since the chambers are independent from one another, when the vapor chamber device is vertically mounted to a heat source, the chambers at an upper portion of the vapor chamber device still contain the working fluid. The working fluid in the vapor chamber device may not all flow to a bottom of the vapor chamber device. Therefore, a contact area between the working fluid and the heat source is increased and heat dissipation efficiency is improved.Type: ApplicationFiled: December 7, 2020Publication date: May 12, 2022Inventors: Pu-Ju LIN, Ying-Chu CHEN, Wei-Ci YE, Chi-Hai KUO, Cheng-Ta KO
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Publication number: 20220130781Abstract: A circuit substrate structure includes a circuit substrate, at least two chips, and a bridge element. The circuit substrate has a first surface and a second surface opposite to each other. The chips are arranged in parallel on the first surface of the circuit substrate and electrically connected to the circuit substrate. The chips have active surfaces, back surfaces opposite to the active surfaces, and side surfaces connecting the active surfaces and the back surfaces. The chips include side circuits. The side circuits are arranged on the side surfaces and have first ends and second ends, the first ends extend to the active surfaces along the side surfaces, and the second ends extend to the back surfaces along the side surfaces. The bridge element is arranged on the back surfaces of the chips and electrically connected to the active surfaces of the chips through the side circuits.Type: ApplicationFiled: January 4, 2022Publication date: April 28, 2022Applicant: Unimicron Technology Corp.Inventors: Tzyy-Jang Tseng, Pu-Ju Lin, Cheng-Ta Ko, John Hon-Shing Lau
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Publication number: 20220108953Abstract: A package structure, including a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips, is provided. The bridge includes a silicon substrate, a redistribution layer, and multiple bridge pads. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The bridge is embedded in the intermediate layer. The bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.Type: ApplicationFiled: May 7, 2021Publication date: April 7, 2022Applicant: Unimicron Technology Corp.Inventors: John Hon-Shing Lau, Cheng-Ta Ko, Pu-Ju Lin, Tzyy-Jang Tseng, Ra-Min Tain, Kai-Ming Yang
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Publication number: 20220068742Abstract: A chip package includes a redistribution layer, a chip, and an encapsulation member. The redistribution layer includes an insulation part, a plurality of first pads and a plurality of second pads, where the insulation part has a first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface. The first pads and the second pads are located at the first surface and the second surface respectively. The chip is disposed on the first surface and electrically connected to the first pads. The encapsulation member wraps the chip and the redistribution layer, and covers the first surface and the side surface, where the encapsulation member exposes the second pads, and the encapsulation member is not flush with the first surface and the side surface.Type: ApplicationFiled: November 4, 2021Publication date: March 3, 2022Inventors: Cheng-Hui WU, Jeng-Ting LI, Ping-Tsung LIN, Kai-Ming YANG, Pu-Ju LIN, Cheng-Ta KO
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Publication number: 20220068872Abstract: A fabrication method of an electronic device bonding structure includes the following steps. A first electronic component including a first conductive bonding portion is provided. A second electronic component including a second conductive bonding portion is provided. A first organic polymer layer is formed on the first conductive bonding portion. A second organic polymer layer is formed on the second conductive bonding portion. Bonding is performed on the first electronic component and the second electronic component through the first conductive bonding portion and the second conductive bonding portion, such that the first electronic component and the second electronic component are electrically connected. The first organic polymer layer and the second organic polymer layer diffuse into the first conductive bonding portion and the second conductive bonding portion after the bonding. An electronic device bonding structure is also provided.Type: ApplicationFiled: September 24, 2020Publication date: March 3, 2022Applicant: Unimicron Technology Corp.Inventors: Chia-Fu Hsu, Kai-Ming Yang, Pu-Ju Lin, Cheng-Ta Ko
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Publication number: 20220069489Abstract: A circuit board structure, including a redistribution circuit structure layer, a build-up circuit structure layer, and a connection structure layer, is provided. The redistribution circuit structure layer includes multiple first connecting pads. The build-up circuit structure layer is disposed on one side of the redistribution circuit structure layer and includes multiple second connecting pads. A line width and a line spacing of the redistribution circuit structure layer are smaller than a line width and a line spacing of the build-up circuit structure layer. The connection structure layer is disposed between the redistribution circuit structure layer and the build-up circuit structure layer, and includes a substrate and multiple conductive paste pillars penetrating the substrate. The first connecting pads are electrically connected to the second connecting pads respectively through the conductive paste pillars.Type: ApplicationFiled: May 13, 2021Publication date: March 3, 2022Applicant: Unimicron Technology Corp.Inventors: John Hon-Shing Lau, Chia-Yu Peng, Kai-Ming Yang, Pu-Ju Lin, Cheng-Ta Ko, Tzyy-Jang Tseng
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Publication number: 20220071010Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first, second and third sub-circuit boards are electrically connected to one another.Type: ApplicationFiled: September 26, 2021Publication date: March 3, 2022Inventors: Tzyy-Jang TSENG, Cheng-Ta KO, Pu-Ju LIN, Chi-Hai KUO, Shao-Chien LEE, Ming-Ru CHEN, Cheng-Chung LO
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Publication number: 20220059498Abstract: A chip package structure includes a substrate, a first chip, a second chip, a bridge, a plurality of first bumps, a plurality of second bumps, a plurality of third bumps and a plurality of solder balls. A first active surface of the first chip and a second active surface of the second chip face a first surface of the substrate. The bridge includes a high-molecular polymer layer and a pad layer located on the high-molecular polymer layer. The first chip is electrically connected to the substrate through the first bumps. The second chip is electrically connected to the substrate through the second bumps. The first chip and the second chip are electrically connected to the pad layer through the third bumps. The first bumps and the second bumps have the same size. The solder balls are disposed on a second surface of the substrate and electrically connected to the substrate.Type: ApplicationFiled: November 15, 2020Publication date: February 24, 2022Applicant: Unimicron Technology Corp.Inventors: Tzyy-Jang Tseng, Pu-Ju Lin, Cheng-Ta Ko, Ra-Min Tain
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Publication number: 20210296291Abstract: A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit layer have been formed on the carrier. A flat structure layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and covers the flat structure layer and a portion of the first dielectric layer. A second patterned circuit layer is formed on the second dielectric layer. The second patterned circuit layer includes a plurality of pads. An orthographic projection of the flat structure layer on the carrier overlaps orthographic projections of the pads on the carrier. A plurality of chips are disposed on the pads. A molding compound is formed to cover the second dielectric layer and encapsulate the chips and the pads.Type: ApplicationFiled: April 13, 2020Publication date: September 23, 2021Applicant: Unimicron Technology Corp.Inventors: Pu-Ju Lin, Chi-Hai Kuo, Kai-Ming Yang, Cheng-Ta Ko
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Publication number: 20210251107Abstract: A vapor chamber structure includes a thermally conductive housing, a capillary structure layer, a grid structure layer, and a working fluid. The thermally conductive housing has a sealed chamber, where a pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer is disposed in the sealed chamber. The grid structure layer is disposed in the sealed chamber and arranged along a first direction. A size of the grid structure layer is less than or equal to a size of the capillary structure layer. The working fluid fills the sealed chamber.Type: ApplicationFiled: September 11, 2020Publication date: August 12, 2021Applicant: Unimicron Technology Corp.Inventors: Ra-Min Tain, Pu-Ju Lin, Cheng-Chung Lo, Chi-Hai Kuo, Cheng-Ta Ko, Tzyy-Jang Tseng, John Hon-Shing Lau
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Publication number: 20210247147Abstract: A vapor chamber structure including a thermally conductive shell, a capillary structure layer, and a working fluid is provided. The thermally conductive shell includes a first thermally conductive portion and a second thermally conductive portion. The first thermally conductive portion has at least one first cavity. The second thermally conductive portion and the first cavity define at least one sealed chamber, and a pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer covers an inner wall of the sealed chamber. The working fluid is filled in the sealed chamber.Type: ApplicationFiled: February 5, 2021Publication date: August 12, 2021Applicant: Unimicron Technology Corp.Inventors: Ra-Min Tain, John Hon-Shing Lau, Pu-Ju Lin, Wei-Ci Ye, Chi-Hai Kuo, Cheng-Ta Ko, Tzyy-Jang Tseng