Abstract: A radio frequency integrated circuit (RFIC), including a power amplifier (PA) connected to an antenna through a first electromagnetic (EM) element, the PA configured to receive a transmit signal from a second EM element, a low noise amplifier (LNA) connected to the first EM element and the second EM element, the power amplifier and the LNA comprising separate amplifier cores, and wherein the first EM element comprises a first plurality of interwound windings occupying a first common area and the second EM element comprises a second plurality of interwound windings occupying a second common area.

Abstract: An oscillation circuit includes: a current mirror circuit outputting a reference current; a charging and discharging circuit charging a first charge storage element by using one of the reference currents or discharging the first charge storage element, to generate a first control voltage; an output stage circuit including a first switch transistor controlled by the first control voltage to output a first oscillation signal; a first resistor; a second resistor; and a diode circuit. The first resistor and the second resistor have same directional temperature drifts, a first resistance of the first resistor is greater than a second resistance of the second resistor, and a first resistance drift of the first resistor with a temperature variation is smaller than a second resistance drift of the second resistor with the temperature variation, such that the effect of the temperature variation on a frequency accuracy is reduced.

Abstract: A delay calibration circuit includes a first delay chain, a second delay chain, and a calibration circuit. The first delay chain includes a plurality of first delay units and delays a clock signal with a first delay to generate a first delay signal. The supply current for each of the first delay units is a first current. The second delay chain includes a plurality of second delay units and a third delay unit. The second delay units delay a first signal with a second delay to generate a second delay signal. The third delay unit delays the second delay signal to generate the third delay signal. The supply current for each unit in the second delay chain is a second current. The calibration circuit adjusts a current ratio of the second current to the first current based on the second delay signal and the third delay signal.

Abstract: In a driving circuit, a drain of first NMOS transistor receives current with a positive temperature coefficient provided by current source, and a gate of first NMOS transistor and a gate of second NMOS transistor are electrically connected to the drain of first NMOS transistor. A drain and a source of second NMOS transistor respectively receive an input voltage and generate an output voltage for driving a load. Two ends of resistor are respectively electrically connected to a source of first NMOS transistor and an emitter of PNP bipolar junction transistor. A base of PNP bipolar junction transistor is electrically connected to a source of second NMOS transistor, and a collector of PNP bipolar junction transistor is electrically connected to a low voltage. By selecting the resistance value of the resistor, an overdrive voltage or a turned-on resistance value of second NMOS transistor is independent of a temperature variation.

Abstract: A low power oscillator circuit with temperature compensation is illustrated. A current supply unit of an oscillator used to output an output current which is proportional to a reference current. As the temperature is increased, both a first threshold and the reference current of a unidirectional conduct in the temperature compensation circuit are decreased. Because a delay time of the oscillating signal is proportional to the first threshold voltage, and the delay time is inversely proportional to the reference current, the effects of the first threshold voltage and the reference current on the delay time are canceled, and the delay time of the oscillating signal is not affected by the temperature.

Abstract: A system and method for testing two-phase liquid cooling are disclosed. The system may include, a liquid storage tank; a power pump having an inlet in communication with an outlet of the liquid storage tank; a regenerator having a first loop and a second loop and a first regulating valve; a preheater and a second regulating valve; a liquid outlet port and a liquid outlet valve; a liquid inlet port and a liquid inlet valve; and a condenser having an inlet in communication with an outlet of the second loop.

Abstract: A rail-to-rail input stage circuit including a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first processing circuit, a second processing circuit, a first voltage adjustment circuit, and a second voltage adjustment circuit is provided. The first P-type transistor and the first N-type transistor are coupled to a first input terminal. The second P-type transistor and the second N-type transistor are coupled to a second input terminal. In response to the voltage of the first terminal being higher than a first threshold value, the first voltage adjustment circuit controls the operation of the first processing circuit. In response to the voltage of the first terminal being lower than a second threshold value, the second voltage adjustment circuit controls the operation of the second processing circuit.

Abstract: This invention relates to methods of producing a population of progenitor T cells comprising differentiating haematopoietic progenitor cells (HPCs) into progenitor T cells in the presence of a pyrimidoindole compound, such as methyl 4-(3-piperidin-1-ylpropylamino)-9H-pyrimido[4,5-b] indole-7-carboxylate (UM729) or (1R,4R)-N1-(2-benzyl-7-(2-methyl-2H-tetrazol-5-yl)-9H-pyrimido[4,5-b]indol-4-yl)cyclohexane-1,4-diamine (UM171). The progenitor T cells may be matured, activated and expanded, for example for use in immunotherapy.

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

Abstract: Disclosed in the present invention are a magnolol and sulforaphane conjugate, and a preparation method and use thereof. The magnolol and sulforaphane conjugate comprises C25H29NO2S2 (CT-1), C25H29NO4S2(CT-2), and C25H29NO3S2(CT-3). By using the drug combination principle, the present invention achieved the first synthesis of the magnolol and sulforaphane conjugate (CT-1, CT-2, CT-3). According to biological evaluation, the conjugate has an antitumor effect remarkably superior to that of magnolol and sulforaphane, has a broad spectrum of antitumor activity and strong druggability. It is an antitumor compound with development potential, and also provides new ideas and approaches for development of a novel antitumor drug.

Abstract: A pump-driven two-phase liquid cooling system, and a liquid supplementation control method for a pump-driven two-phase liquid cooling system are disclosed. The pump-driven two-phase liquid cooling system may include a pump-driven two-phase liquid circulation loop, where a pump, an evaporator, and a condenser are sequentially arranged in the pump-driven two-phase liquid circulation loop; a first liquid storage tank arranged at a front end of the pump; and a second liquid storage tank in fluid communication with the first liquid storage tank through a first connecting pipeline; where the second liquid storage tank is provided with a first liquid filling port, and the first connecting pipeline is provided with a first valve configured to isolate the second liquid storage tank from the first liquid storage tank.

Abstract: A referential voltage generating device includes a bandgap-voltage generating unit, a control-comparison unit, a difference current generating unit and a referential voltage generating unit. The bandgap-voltage generating unit generates a second proportional to absolute temperature (PTAT) current and a bandgap-voltage based on a first PTAT current and a complementary to an absolute temperature (CTAT) voltage, both of which are generated in the bandgap-voltage generating unit. The control-comparison unit generates a PTAT voltage based on the second PTAT current, and generates a control voltage based on a difference voltage value between the PTAT voltage and the bandgap voltage. The difference current generating unit generates the difference current based on the control voltage, wherein the difference current is proportional to an absolute voltage value of the control voltage. The referential voltage generating unit generates a referential voltage based on the bandgap voltage and the differential current.

Abstract: An oscillator equipped with a temperature compensation circuit is illustrated. Through the temperature compensation circuit, a transistor of a current mirror circuit of the oscillator which outputs a reference current to a voltage matching circuit is controlled by the temperature compensation voltage. Both of the temperature compensation voltage and a reference current decrease as the temperature rises, and a delay time of the oscillation voltage is proportional to the temperature compensation voltage and inversely proportional to the reference current. Therefore, the effects of temperature on the delay time just cancel each other out. The delay time of the oscillating voltage is related to the frequency of the clock signal. Therefore, if the delay time of the oscillating voltage is not affected by temperature, the frequency of the clock signal will not be affected by temperature.

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: A method for rock identification includes the steps of receiving a rock slice image transmitted by an image acquisition device, generating a geometric feature, a mineral feature and a structural feature corresponding to a rock slice based on the rock slice image, and generating an identification result of the rock slice based on the geometric feature, the mineral feature and the structural feature. After the rock slice image is obtained, the rock slice image is subject to feature extraction based on three dimensions, i.e., the geometric feature, the mineral feature and the structural feature, the properties of rock are determined based on multiple dimensional features, and finally the identification result comprising a textual description is generated. After a microscopic visual image corresponding to the rock slice is obtained, feature extraction based on multiple dimensions is performed on the image, and the rock slice is identified with reference to multi-dimensional features.

Abstract: A low power oscillator circuit with temperature compensation is illustrated. A current supply unit of an oscillator used to output an output current which is proportional to a reference current. As the temperature is increased, both a first threshold and the reference current of a unidirectional conduct in the temperature compensation circuit are decreased. Because a delay time of the oscillating signal is proportional to the first threshold voltage, and the delay time is inversely proportional to the reference current, the effects of the first threshold voltage and the reference current on the delay time are canceled, and the delay time of the oscillating signal is not affected by the temperature.

Abstract: Disclosed are a heat dissipation apparatus and an electronic device. The heat dissipation apparatus may include: a cooling component, comprising at least two cooling plates in which a flow channel for containing a working medium is arranged; and a first tube, through which the cooling plates are connected, allowing the flow channels of the cooling plates to be communicated with each other, at least part of the first tube being an extendable corrugated tube.

Abstract: In a driving circuit, a drain of first NMOS transistor receives current with a positive temperature coefficient provided by current source, and a gate of first NMOS transistor and a gate of second NMOS transistor are electrically connected to the drain of first NMOS transistor. A drain and a source of second NMOS transistor respectively receive an input voltage and generate an output voltage for driving a load. Two ends of resistor are respectively electrically connected to a source of first NMOS transistor and an emitter of PNP bipolar junction transistor. A base of PNP bipolar junction transistor is electrically connected to a source of second NMOS transistor, and a collector of PNP bipolar junction transistor is electrically connected to a low voltage. By selecting the resistance value of the resistor, an overdrive voltage or a turned-on resistance value of second NMOS transistor is independent of a temperature variation.

Abstract: A comparator module for an oscillator is disclosed. The comparator module has a function provided by two independent comparators that are combined together to share the same bias current source, so that an operation current of the oscillator may be reduced, and the circuit area and power consumption may be effectively reduced. Further, compared to the conventional design that one of the two comparators compares a first voltage with a reference voltage and the other one of the two comparators compares a second voltage with the reference voltage and the time points at which the first voltage and the second voltage are a logic high level are different, three transistors of the disclosed comparator module are designed into two equivalent differential pairs and share a bias current source.