Patents by Inventor Cheng Tsai

Cheng Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200235101
    Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.
    Type: Application
    Filed: April 7, 2020
    Publication date: July 23, 2020
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Cheng Tsai, Chih-Chi Cheng, Chia-Wei Wu, Ger-Pin Lin
  • Patent number: 10709027
    Abstract: A circuit board module for being assembled to a case is provided. The circuit board module includes an electronic connector and a circuit board. The electronic connector is fixed to the circuit board. The circuit board has at least one first slot. The at least one first slot is configured for a fixing element to pass through and for the circuit board to be assembled to a case. The size of the at least one first slot allows the fixing element to move in a direction parallel to a surface of the circuit board in the at least one first slot. An electronic device having the circuit board module is also provided.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: July 7, 2020
    Assignee: PEGATRON CORPORATION
    Inventors: Wen-Hsien Tsao, Ho-Ching Huang, Wen-Cheng Tsai
  • Patent number: 10658365
    Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 19, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Cheng Tsai, Chih-Chi Cheng, Chia-Wei Wu, Ger-Pin Lin
  • Patent number: 10659097
    Abstract: A testing system includes: a bilinear polarized antenna for receiving and dividing a circularly polarized radio wave associating with a horizontal and a vertical polarization path of an object-to-be-tested into a first and a second high frequency signal; a phase retarder for delaying a phase of the first high frequency signal by 90 degrees to form a first high frequency signal with a phase delay of 90 degrees; a power splitter for receiving or synthesizing the first high frequency signal with the phase delay of 90 degrees and the second high frequency signal; and a high frequency signal transceiver for measuring power of the first high frequency signal with the phase delay of 90 degrees and the second high frequency signal and determining states of the horizontal and vertical polarization paths of the object-to-be-tested based on the power. Therefore, the testing system can speed up testing of the object-to-be-tested.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: May 19, 2020
    Inventors: Bo-Siang Fang, Kuan-Ta Chen, Ying-Wei Lu, Chia-Chu Lai, Cheng-Tsai Hsieh
  • Patent number: 10656637
    Abstract: A monitoring system applied to a shaping machine having a high speed electricity meter. The monitoring system includes a current obtaining device and an analyzing device. The current obtaining device is coupled to the high speed electricity meter to obtain a plurality of current signals from the operated shaping machine and in respond to the shaping machine executes a machining program, the current obtaining device extracts current variation data from the current signals. The machining program corresponds to a piece of the current variation data. The piece of the current variation datum comprises a maximum current and an occurring time that the maximum current being recorded. The analyzing device is configured to calculate a gap, based on the maximum currents and the occurring times corresponding to at least two successive machining programs. In respond to the gap time exceeding a predetermined threshold, the analyzing device generates a warning signal.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: May 19, 2020
    Assignee: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Jun-Ren Chen, Hung-Sheng Chiu, Chih-Chieh Lin, Chien-Chih Lu, Cheng-Tsai Lai, Kun-Yu Lin
  • Patent number: 10660246
    Abstract: An electromagnetic shielding assembly configured to be disposed on a circuit board with at least one electronic component includes a plurality of shielding housings. The shielding housings form a gap therebetween. Each of the shielding housings has a first opening adjoining the gap. The shielding housings are configured to accommodate part of the electronic component. The electronic component is configured to pass through the first openings of the shielding housings and the gap.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: May 19, 2020
    Assignee: PEGATRON CORPORATION
    Inventors: Mei-Hsueh Huang, Jr-Hung Huang, Wen-Cheng Tsai
  • Publication number: 20200154615
    Abstract: An electromagnetic shielding assembly configured to be disposed on a circuit board with at least one electronic component includes a plurality of shielding housings. The shielding housings form a gap therebetween. Each of the shielding housings has a first opening adjoining the gap. The shielding housings are configured to accommodate part of the electronic component. The electronic component is configured to pass through the first openings of the shielding housings and the gap.
    Type: Application
    Filed: November 1, 2019
    Publication date: May 14, 2020
    Inventors: Mei-Hsueh HUANG, Jr-Hung HUANG, Wen-Cheng TSAI
  • Publication number: 20200105763
    Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 2, 2020
    Inventors: Po-Han Wu, Li-Wei Feng, Shih-Han Hung, Fu-Che Lee, Chien-Cheng Tsai
  • Publication number: 20200072886
    Abstract: A testing fixture used in an antenna testing process is provided. A cover unit having a second antenna portion is arranged on a base unit configured for an electronic structure having a first antenna portion to be placed thereon. The cover unit includes a non-metal interposing portion configured for pressing the electronic structure to separate the second antenna portion from the first antenna portion. Therefore, when the antenna testing process is performed on the electronic structure, a metal shielding effect is avoided, and an over the air testing environment is provided.
    Type: Application
    Filed: May 9, 2019
    Publication date: March 5, 2020
    Inventors: Bo-Siang Fang, Cheng-Tsai Hsieh, Kuan-Ta Chen, Ying-Wei Lu
  • Patent number: 10579569
    Abstract: A universal serial bus type-C interface circuit and a pin bypass method thereof are provided. The interface circuit includes a first configuration channel pin, a second configuration channel pin, a port manager and a port controller. The port manager has a first signal terminal and a second signal terminal. The port controller includes a multiplexer circuit and a control logic circuit. The multiplexer circuit is coupled to the first configuration channel pin, the second configuration channel pin, the first signal terminal and the second signal terminal. The control logic circuit is coupled to the multiplexer circuit and provides a multiplexer control signal to the multiplexer circuit in response to a switching request. The multiplexer circuit couples the first configuration channel pin and the second configuration channel pin to the first signal terminal and the second signal terminal respectively according to the multiplexer control signal.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: March 3, 2020
    Assignee: Nuvoton Technology Corporation
    Inventors: Chao-Chiuan Hsu, Lian-Cheng Tsai, Shih-Hsuan Yen
  • Patent number: 10580499
    Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: March 3, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Pang Lu, Chi-Hsiu Hsu, Chung-Hao Chen, Ya-Nan Mou, Chung-Cheng Tsai
  • Patent number: 10543657
    Abstract: In one example, a housing for an electronic device may be disclosed which may include a first multi-layer structure. The first multi-layer structure may include a first layer and a second layer formed on the first layer. Each of the first layer and the second layer may include a plurality of protruding features and a plurality of recessing features on an edge of the first layer and the second layer. At least one of the plurality of recessing features of one layer may intersect at least one of the plurality of protruding features of other layer.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: January 28, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Hsiu-Pen Lin, Kun-Cheng Tsai, Chienchih Chiu
  • Patent number: 10546537
    Abstract: A display device includes a display panel and display drivers disposed on the display panel. The distance between a first display driver and a second display driver of the display drivers is greater than the distance between a second display driver and a third display driver of the display drivers. The display panel includes a curved segment adjacent to an area between the first display driver and the second display driver.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: January 28, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Yi-Cheng Tsai, Cheng-Tso Chen, Hui-Min Huang, Li-Wei Sung
  • Patent number: 10541485
    Abstract: An on-board diagnostic connector terminal is provided, including a plurality of first pins, a plurality of second pins and a substrate. Each first pin includes a first section and a second section. The first section connects to the second section. The first section includes a first connection end, and the second section includes a first soldering end. Each second pin includes a second connection end and a second soldering end. The first pins and the second pins are disposed on the substrate. The first soldering ends and the second soldering ends are arranged on a first straight line. At least one first connection end and the second connection end corresponding thereto are arranged linearly in a first direction. The first direction is perpendicular to the first straight line.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: January 21, 2020
    Assignee: WISTRON NEWEB CORP.
    Inventors: Tien-Chun Hung, Guo-Cheng Tsai, Cheng-Huang Chen
  • Patent number: 10529719
    Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: January 7, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Han Wu, Li-Wei Feng, Shih-Han Hung, Fu-Che Lee, Chien-Cheng Tsai
  • Patent number: 10529296
    Abstract: To a unit circuit, provided are a transistor to which a first clock signal is supplied, a transistor for applying an off-level voltage to a first node, a transistor for applying the off-level voltage to a second node, a transistor for applying an on-level voltage to the second node based on a clock signal being ahead of the first clock signal in a forward direction scanning, a transistor for applying the on-level voltage to the second node based on a clock signal being ahead of the first clock signal in a backward direction scanning, and a circuit for controlling a voltage of the first node based on output signals of the unit circuits in a front-side stage and a back-side stage. The unit circuit is configured so that a voltage of the second node is changed to an ON level and an OFF level while a voltage of the first node is in the OFF level and the voltage of the second node is in the ON level when the first clock signal is changed to the ON level while the voltage of the first node is in the OFF level.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: January 7, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yi-Cheng Tsai, Satoshi Horiuchi
  • Patent number: 10475794
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first bit line structure on a substrate; forming a first spacer adjacent to the first bit line structure; forming an interlayer dielectric (ILD) layer adjacent to the first spacer; removing part of the ILD layer and part of the first spacer to expose a sidewall of the first bit line structure; and forming a first storage node contact isolation structure adjacent to the first bit line structure, wherein the first storage node contact isolation structure contacts the first bit line structure and the first spacer directly.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: November 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Han Wu, Fu-Che Lee, Chien-Cheng Tsai, Tzu-Tsen Liu, Wen-Chieh Lu
  • Publication number: 20190304909
    Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
    Type: Application
    Filed: June 19, 2019
    Publication date: October 3, 2019
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Chien-Cheng Tsai, Feng-Ming Huang
  • Publication number: 20190296019
    Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.
    Type: Application
    Filed: April 24, 2018
    Publication date: September 26, 2019
    Inventors: Po-Han Wu, Li-Wei Feng, Shih-Han Hung, Fu-Che Lee, Chien-Cheng Tsai
  • Publication number: 20190265830
    Abstract: A touch control device with ESD protection includes a touch display panel, a switching unit, a touch electrode and a ground electrode. An ESD protection electrode is provided around at least one periphery of the touch display panel. A scanning period of the ESD protection electrode is divided into touch periods and ESD periods. When the scanning period of the ESD protection electrode is during the touch periods, the ESD protection electrode is used as touch electrodes for sensing touch events made by a user on the touch display panel. When the scanning period of the ESD protection electrode is during the ESD periods, the ESD protection electrode is used as ESD protection electrodes for dissipating ESD on the touch display panel in order to protect signal elements inside the touch display panel. The ESD protection electrode is therefore used for not only ESD protection, but also touch sensing.
    Type: Application
    Filed: February 27, 2018
    Publication date: August 29, 2019
    Inventors: Chien-Hsun Chen, Yung-Cheng Tsai, Chien-Le Li, Shih-Hong Jhang, You-Hong Jhang