SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a substrate, first and second body regions, a well region, a source region, a drain region, and first and second doped regions. The first and second body regions are disposed in first and second regions respectively. The well region is disposed in the first and second regions and between the first and second body regions. First and second portions of the source region are disposed in the first and second body regions respectively. The drain region is disposed on the well region. The first doped region is disposed in the well region. The second doped region is disposed on the first doped region. A first portion of the first doped region and a first portion of the second doped region are disposed in the well region of the first region and extend toward the first body region and out of the well region.
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The invention relates to a semiconductor device, and more particularly to a method of manufacturing a power semiconductor device having a depletion structure and an enhancement structure.
Description of the Related ArtGenerally, in a flyback power supplier, there is a depletion-type element used to convert an external alternating-current (AC) voltage to a direct-current (DC) voltage which serves as the supply voltage for the internal elements of the flyback power supplier. Moreover, there is also a power element having a small source-drain resistance in the flyback power supplier to transfer a voltage signal on the primary side to the circuit on the secondary side. The depletion-type element and the power element are generally implemented by two independence elements, which unfortunately increases the area of the circuitry. Moreover, after these elements are packaged, two lines are required to connect the depletion-type element to the drain of the power element, which increase the cost of the circuitry.
BRIEF SUMMARY OF THE INVENTIONAn exemplary embodiment of a semiconductor device is provided. The semiconductor device comprises a substrate, a first body region, a second body region, a well region, a source region, a drain region, a first doped region, and a second doped region. The substrate has a first conductive type and comprises a first region and a second region. The first body region is disposed in the first region of the substrate. The second body region is disposed in the second region of the substrate. The second body region has the first conductive type. The well region is disposed in the first region and the second region of the substrate and between the first body region and the second body region. The well region has a second conductive type opposite to the first conductive type. The source region comprises a first portion disposed in the first body region and a second portion disposed in the second body region. The drain region is disposed on the well region. The first doped region is disposed in the well region. The first doped region has the first conductive type. The second doped region is disposed in the well region and stacked on the first doped region. The second doped region has the second conductive type. A first portion of the first doped region and a first portion of the second doped region are disposed in the well region of the first region of the substrate and extend toward the first body region and out of the well region.
An exemplary embodiment of a method for manufacturing a semiconductor device is provided. The method comprises steps of forming a substrate having a first conductive type, wherein the substrate comprises a first region and a second region; forming a first body region in the first region of the substrate; forming a second body region in the second region of the substrate, wherein the second body region has the first conductive type; forming a well region in the first region and the second region of the substrate, wherein the well region is formed between the first body region and the second body region and has a second conductive type opposite to the first conductive type; forming a source region, wherein a first portion of the source region is formed in the first body region, and a second portion of the source region is formed in the second body region; forming a drain region disposed on the well region; implanting a first dopant in the well region to form a first doped region, wherein the first doped region has the first conductive type; and implanting a second dopant in the well region and on the first doped region to form a second doped region, wherein the second doped region has the second conductive type. A first portion of the first doped region and a first portion of the second doped region are formed in the well region of the first region of the substrate and extend toward the first body region and out of the well region.
The invention can be more fully understood by referring to the following detailed description and examples with references made to the accompanying drawings, wherein:
The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention.
It should be noted that the elements or devices in the drawings of the present disclosure may be present in any form or configuration known to those skilled in the art. In addition, the expression “a layer overlying another layer”, “a layer is disposed above another layer”, “a layer is disposed on another layer” and “a layer is disposed over another layer” may indicate not only that the layer directly contacts the other layer, but also that the layer does not directly contact the other layer, there being one or more intermediate layers disposed between the layer and the other layer.
Referring to
Moreover, a gate insulating layer 21 is disposed in the regions 10D and 10E of the semiconductor substrate 10 and covers one portion of the field insulating layer 16. In the region 10D, the gate insulating layer 21 extends in the direction from the field insulating layer 16 to the body region 12 to cover the N+-type doped region 18. In the region 10E, the gate insulating layer 21 extends in the direction from the field insulating layer 16 to the body region 14 to cover one portion of the well region 11 and one portion of the semiconductor substrate 10. A gate structure 20 is disposed on the gate dielectric layer. According to the disposition relationship between the field insulating layer 16, the gate insulating layer 21, and the N+-type doped region 18, one portion of the N+-type doped region 18 in the region 10D is covered by one portion of the gate insulating layer 21, while the N+-type doped region 18 in the region 10E is not covered by the gate insulating layer 21. Referring to
The manufacturing method for the power semiconductor device 1 will be described in the following by referring to the corresponding drawings. Referring to
Then, the exemplary steps for forming body regions 12 and 14 will be described by referring to
The exemplary steps for forming a P+-type region 17 and an N+-type region 18 will be described by referring to
Then, referring to
Continuously referring to
Referring to
In an embodiment, the power semiconductor device 1 has a finger-type structure. As shown in
In the above embodiments, the body region 12 in the region 10D is formed by the P+-type doped region 12A and the N+-type doped region 12B, and the contact regions 13A and 13B are disposed in the doped regions 12A and 12B respectively. In other embodiments, as shown in
In the above embodiments, the power semiconductor devices are implemented by N-type devices. However, in other embodiments, the power semiconductor devices can be implemented by P-type devices. The structures of the P-type power semiconductor devices are similar to the structures of the above N-type power semiconductor devices, but the conductive types of the material of the P-type power semiconductor devices is opposite to the conductive types of the material of the N-type power semiconductor devices.
While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). For example, it should be understood that the system, device and method may be realized in software, hardware, firmware, or any combination thereof. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims
1. A semiconductor device, comprising:
- a substrate having a first conductive type and comprising a first region and a second region;
- a first body region disposed in the first region of the substrate;
- a second body region, disposed in the second region of the substrate, having the first conductive type;
- a well region, disposed in the first region and the second region of the substrate and between the first body region and the second body region, having a second conductive type opposite to the first conductive type;
- a source region comprising a first portion disposed in the first body region and a second portion disposed in the second body region;
- a drain region disposed on the well region;
- a first doped region, disposed in the well region, having the first conductive type; and
- a second doped region, disposed in the well region and stacked on the first doped region, having the second conductive type,
- wherein a first portion of the first doped region and a first portion of the second doped region are disposed in the well region of the first region of the substrate and extend toward the first body region and out of the well region.
2. The semiconductor device as claimed in claim 1, wherein the first portion of the first doped region and the first portion of the second doped region extend out of the well region and contact the first body region.
3. The semiconductor device as claimed in claim 2, wherein a second portion of the first doped region and a second portion of the second doped region are disposed in the second region of the substrate and aligned with a doped-region boundary, and there is a space distance between the doped-region boundary and the second body region.
4. The semiconductor device as claimed in claim 1, wherein a second portion of the first doped region and a second portion of the second doped region are disposed in the second region of the substrate and totally disposed in the well region.
5. The semiconductor device as claimed in claim 4, wherein the second portion of the first doped region and the second portion of the second doped region are aligned with a doped-region boundary, and the doped-region boundary is in the well region.
6. The semiconductor device as claimed in claim 1, further comprising:
- a gate structure disposed on the first doped region,
- wherein the first portion of the source region, the drain region in the first region of the substrate, and the gate structure disposed on the first portion of the first doped region form a depletion transistor.
7. The semiconductor device as claimed in claim 6, wherein a second portion of the first doped region is disposed in the second region of the substrate, and the second portion of the source region, the drain region in the second region of the substrate, and the gate structure formed on the second portion of the first doped region form an enhancement transistor.
8. The semiconductor device as claimed in claim 1, further comprising:
- an insulating layer disposed on the well region;
- a gate insulating layer covering a portion of the insulating layer and extending toward the first body region to cover the first portion of the second doped region; and
- a gate structure disposed on the gate insulating layer.
9. The semiconductor device as claimed in claim 8, wherein a second portion of the second doped region is disposed in the second region of the substrate, and the gate insulating layer extends toward the second body region to cover a portion of the well region.
10. The semiconductor device as claimed in claim 1, wherein source region comprises:
- a first contact region having the second conductive type; and
- a second contact region having the first conductive type,
- wherein the first contact region is disposed between the well region and the second contact region.
11. The semiconductor device as claimed in claim 10, wherein the first body region comprises:
- a third doped region, disposed in the first region of the substrate, having the second conductive type; and
- a fourth doped region, disposed in the first region and the second region of the substrate, having the first conductive type,
- wherein the first contact region of the first portion of the source region is disposed in the third doped region, and the second contact region of the first portion of the source region is disposed in the fourth doped region.
12. The semiconductor device as claimed in claim 11, wherein the first contact region and the second contact region of the second portion of the source region are disposed in the fourth doped region.
13. The semiconductor device as claimed in claim 1, wherein the first conductive type is P type, and the second conductive type is N type.
14. The semiconductor device as claimed in claim 1, wherein the first conductive type is N type, and the second conductive type is P type.
15. The semiconductor device as claimed in claim 1, wherein the drain region comprises:
- a contact region, disposed in the first region and the second region of the substrate, having the second conductive type, and
- wherein the semiconductor device further comprises:
- an inter-connection line connected to the contact region in the first region of the substrate and the contact region in the second region of the substrate.
16. A method for manufacturing a semiconductor device, comprising:
- forming a substrate having a first conductive type, wherein the substrate comprises a first region and a second region;
- forming a first body region in the first region of the substrate;
- forming a second body region in the second region of the substrate, wherein the second body region has the first conductive type;
- forming a well region in the first region and the second region of the substrate, wherein the well region is formed between the first body region and the second body region and has a second conductive type opposite to the first conductive type;
- forming a source region, wherein a first portion of the source region is formed in the first body region, and a second portion of the source region is formed in the second body region;
- forming a drain region disposed on the well region;
- implanting a first dopant in the well region to form a first doped region, wherein the first doped region has the first conductive type; and
- implanting a second dopant in the well region and on the first doped region to form a second doped region, wherein the second doped region has the second conductive type,
- wherein a first portion of the first doped region and a first portion of the second doped region are formed in the well region of the first region of the substrate and extend toward the first body region and out of the well region.
17. The method as claimed in claim 16, wherein the first portion of the first doped region and the first portion of the second doped region extend out of the well region and contact the first body region.
18. The method as claimed in claim 17, wherein a second portion of the first doped region and a second portion of the second doped region are disposed in the second region of the substrate and aligned with a doped-region boundary, and there is a space distance between the doped-region boundary and the second body region.
19. The method as claimed in claim 16, wherein a second portion of the first doped region and a second portion of the second doped region are disposed in the second region of the substrate and totally disposed in the well region.
20. The method as claimed in claim 19, wherein the second portion of the first doped region and the second portion of the second doped region are aligned with a doped-region boundary, and the doped-region boundary is in the well region.
21. The method as claimed in claim 16, further comprising:
- forming a gate structure in the first doped region,
- wherein the first portion of the source region, the drain region in the first region of the substrate, and the gate structure formed on the first portion of the first doped region form a depletion transistor.
22. The method as claimed in claim 21, wherein a second portion of the first doped region is formed in the second region of the substrate, and the second portion of the source region, the drain region in the second region of the substrate, and the gate structure formed on the second portion of the first doped region form an enhancement transistor.
23. The method as claimed in claim 16, further comprising:
- forming an insulating layer on the well region;
- forming a gate insulating layer to cover a portion of the insulating layer, wherein the gate insulating layer extends toward the first body region to cover the first portion of the second doped region; and
- forming a gate structure on the gate insulating layer.
24. The method as claimed in claim 23, wherein the gate insulating layer extends toward the second body region to cover a portion of the well region.
25. The method as claimed in claim 16, wherein forming the source region comprises:
- implanting the second dopant to form a first contact region, wherein the first contact region has the second conductive type; and
- implanting the first dopant to form a second contact region, wherein the first contact region has the first conductive type,
- wherein the first contact region is disposed between the well region and the second contact region.
26. The method as claimed in claim 25, wherein forming the first body region comprises:
- implanting the second dopant in the first region of the substrate to form a third doped region wherein the third doped region has the second conductive type; and
- implanting the first dopant in the first region and the second region of the substrate to form a fourth doped region, wherein the fourth doped region has the first conductive type,
- wherein the first contact region of the first portion of the source region is formed in the third doped region, and the second contact region of the first portion of the source region is formed in the fourth doped region.
27. The method as claimed in claim 26, wherein the first contact region and the second contact region of the second portion of the source region are formed in the fourth doped region.
28. The method as claimed in claim 16, wherein the first conductive type is P type, and the second conductive type is N type.
29. The method as claimed in claim 16, wherein the first conductive type is N type, and the second conductive type is P type.
30. The method as claimed in claim 16, wherein forming the drain region comprises:
- forming a contact region in the first region and the second region of the substrate, wherein the contact region has the second conductive type, and
- wherein the method further comprises:
- connecting the contact region in the first region of the substrate with the contact region in the second region of the substrate through an inter-connection line.
Type: Application
Filed: Sep 8, 2017
Publication Date: Mar 14, 2019
Applicant: Vanguard International Semiconductor Corporation (Hsinchu)
Inventors: Cheng-Tsung WU (Taipei City), Shin-Cheng LIN (Tainan City), Wen-Hsin LIN (Jhubei City), Yu-Hao HO (Keelung City)
Application Number: 15/699,572