Abstract: A memory device includes a first memory cell, a second memory cell, a word line, a bit line, a first source line and a second source line. The first memory cell includes a control terminal, a data terminal and a source terminal. The first memory cell includes a control terminal, a data terminal and a source terminal. The word line is coupled to the control terminal of the first memory cell and the control terminal of the second memory cell. The bit line is coupled to the data terminal of the first memory cell and the data terminal of the second memory cell. The first source line is coupled to the source terminal of the first memory cell for receiving a first source voltage. The second source line is coupled to the source terminal of the second memory cell for receiving a second source voltage.

Abstract: Prosthetic heart valve assemblies and methods, apparatus, and systems used to deliver a prosthetic heart valve assembly. A prosthetic heart valve assembly includes an inner frame, a prosthetic leaflet section disposed within the inner frame extending between in inflow row of cells and an outflow row of cells of the inner frame, and an outer support stent. The inner frame is disposed within the outer support stent, and the outer support stent is coupled and/or fastened to the inner frame. The outer support stent includes a plurality leaflet capturing arms for capturing native leaflets between the leaflet capturing arms and a portion of the prosthetic heart valve assembly when the prosthetic heart valve assembly is implanted in a native valve. For example, the native leaflets can be frictionally secured between the leaflet capturing arms of the support stent and the inner frame.

Abstract: A MRAM layout structure with multiple unit cells, including a first word line, a second word line and a third word line extending through active areas, wherein two ends of a first MTJ are connected respectively to a second active area and one end of a second MTJ, and two ends of a third MTJ are connected respectively to a third active area and one end of a fourth MTJ, and a first bit line and a second bit line connected respectively to the other end of the second MTJ and the other end of the fourth MTJ.

Abstract: A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.

Abstract: Provided is a semiconductor structure including a circuit layer, an island-shaped conductive layer, a MRAM cell, a bit line and a conductive via. The circuit layer is disposed on a substrate. The island-shaped conductive layer is disposed on the circuit layer. The MRAM cell is disposed between the island-shaped conductive layer and the circuit layer, and is electrically connected to the island-shaped conductive layer and the circuit layer. The bit line is disposed on the island-shaped conductive layer. The conductive via is disposed between the bit line and the island-shaped conductive layer. The island-shaped conductive layer is in contact with a top surface of the MRAM cell.

Abstract: An anastomosis set for anastomosing a first end to be anastomosed with a second end to be anastomosed, such anastomosis set comprising: a first manipulator, with a first telescoping part at a distal end thereof, the first telescoping part is used for telescoping toward the first end to be anastomosed; a second manipulator, with a second telescoping part at a distal end thereof, the second telescoping part is used for telescoping toward the second end to be anastomosed; and an anastomosis mechanism for anastomosing the first end to be anastomosed with the second end to be anastomosed; the first manipulator including a first exit part through which the first manipulator will be removed from the first end to be anastomosed after anastomosing; the second manipulator has a second exit part, through which the second manipulator will be removed from the second end to be anastomosed after anastomosing.

Abstract: Prosthetic heart valve assemblies and methods, apparatus, and systems used to deliver a prosthetic heart valve assembly. A prosthetic heart valve assembly includes an inner frame, a prosthetic leaflet section disposed within the inner frame extending between in inflow row of cells and an outflow row of cells of the inner frame, and an outer support stent. The inner frame is disposed within the outer support stent, and the outer support stent is coupled and/or fastened to the inner frame. The outer support stent includes a plurality leaflet capturing arms for capturing native leaflets between the leaflet capturing arms and a portion of the prosthetic heart valve assembly when the prosthetic heart valve assembly is implanted in a native valve. For example, the native leaflets can be frictionally secured between the leaflet capturing arms of the support stent and the inner frame.

Abstract: A transistor with a fin structure and a nanosheet includes a fin structure. A first gate device is disposed on the fin structure. A first source/drain layer is disposed at one side of the first gate device. A first source/drain layer is on the fin structure and extends into the fin structure. A second source/drain layer is disposed at another side of the first gate device. The second source/drain layer is on the fin structure and extends into the fin structure. A nanosheet is disposed above the first gate device, between the first source/drain layer and the second source/drain layer, and contacts the first source/drain layer and the second source/drain layer. A second gate device surrounds the nanosheet.

Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems used to deliver a prosthetic heart valve to a deficient valve. In one embodiment, for instance, a support structure and an expandable prosthetic valve are advanced through the aortic arch of a patient using a delivery system. The support structure is delivered to a position on or adjacent to the surface of the outflow side of the aortic valve (the support structure defining a support-structure interior). The expandable prosthetic valve is delivered into the aortic valve and into the support-structure interior. The expandable prosthetic heart valve is expanded while the expandable prosthetic heart valve is in the support-structure interior and while the support structure is at the position on or adjacent to the surface of the outflow side of the aortic valve, thereby causing one or more native leaflets of the aortic valve to be frictionally secured between the support structure and the expanded prosthetic heart valve.

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.

Abstract: A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.

Abstract: An anastomosis set comprising: a first manipulator, with a first telescoping part at a distal end thereof, the first telescoping part is used for telescoping toward the first end to be anastomosed; a second manipulator, with a second telescoping part at a distal end thereof, the second telescoping part is used for telescoping toward the second end to be anastomosed; an anastomosis mechanism for anastomosing the first end with the second end; the first manipulator including a first exit part through which the first manipulator will be removed from the first end to be anastomosed after anastomosing; the second manipulator has a second exit part, through which the second manipulator will be removed from the second end to be anastomosed after anastomosing; an anastomotic auxiliary having with a first embedding end and a second embedding end; wherein the first embedding end is configured to embed into a first end of a blood vessel to be anastomosed, and the second embedding end is configured to embed into a second

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.

Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems used to deliver a prosthetic heart valve assembly. In embodiments, a prosthetic heart valve assembly, including a self-expandable support structure and a self-expanding heart valve, are advanced through the aortic arch of a patient using a delivery system. The support structure, which includes a plurality leaflet retaining arms, is at least partially expanded and positioned on or adjacent to the outflow side of the aortic valve. The prosthetic heart valve is positioned in the aortic valve. The prosthetic heart valve is expanded while it is within an interior of the support structure and while the support structure is positioned on or adjacent to the outflow side of the aortic valve, thereby causing one or more native leaflets of the aortic valve to be frictionally secured between the arms of the support structure and the expanded prosthetic heart valve.

Abstract: A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region.

Abstract: A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region.

Abstract: A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.

Abstract: A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.