Patents by Inventor Cheng-Tung Huang

Cheng-Tung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10510664
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
  • Patent number: 10500047
    Abstract: Representative embodiments of methods, apparatus, and systems used to deliver a prosthetic heart valve to a deficient valve are disclosed. In one embodiment, for instance, a support structure and an expandable prosthetic valve are delivered to a position on or adjacent to the surface of the outflow side of the aortic valve (the support structure defining a support-structure interior) via a delivery system. The expandable prosthetic valve is delivered into the aortic valve and into the support-structure interior. The expandable, prosthetic heart valve is expanded while the expandable prosthetic heart valve is in the support-structure interior and while the support structure is at the position on or adjacent to the surface of the outflow side of the aortic valve, thereby causing one or more native leaflets of the aortic valve to be frictionally secured between the support structure and the expanded prosthetic heart valve.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: December 10, 2019
    Assignee: Edwards Lifesciences Corporation
    Inventors: Christopher J. Olson, Glen Thomas Rabito, Dustin P. Armer, Minh T. Ma, Devin H. Marr, Cheng-Tung Huang, Hiroshi Okabe, Kevin M. Stewart, Alison S. Curtis, Philip P. Corso, Jr.
  • Patent number: 10325994
    Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tang Peng, Tai-Chun Huang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Li-Ting Wang, Chien-Hsun Wang, Huan-Just Lin, Yung-Cheng Lu, Tze-Liang Lee
  • Patent number: 10312235
    Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: June 4, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Yin Weng, Cheng-Tung Huang, Wei-Heng Hsu, Yu-Ming Lin, Ya-Ru Yang
  • Publication number: 20190006360
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.
    Type: Application
    Filed: July 27, 2017
    Publication date: January 3, 2019
    Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
  • Patent number: 10056463
    Abstract: A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 21, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Su Xing, Hsueh-Wen Wang, Chien-Yu Ko, Yu-Cheng Tung, Jen-Yu Wang, Cheng-Tung Huang, Yu-Ming Lin
  • Publication number: 20180166444
    Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.
    Type: Application
    Filed: February 8, 2018
    Publication date: June 14, 2018
    Inventors: Wen-Yin Weng, Cheng-Tung Huang, Wei-Heng Hsu, Yu-Ming Lin, Ya-Ru Yang
  • Patent number: 9929154
    Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: March 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Yin Weng, Cheng-Tung Huang, Wei-Heng Hsu, Yu-Ming Lin, Ya-Ru Yang
  • Publication number: 20180006129
    Abstract: A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.
    Type: Application
    Filed: June 20, 2017
    Publication date: January 4, 2018
    Inventors: Su Xing, Hsueh-Wen Wang, Chien-Yu Ko, Yu-Cheng Tung, Jen-Yu Wang, Cheng-Tung Huang, Yu-Ming Lin
  • Patent number: 9793296
    Abstract: A method for fabricating substrate of a semiconductor device includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: October 17, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Yin Weng, Cheng-Tung Huang, Ya-Ru Yang, Yi-Ting Wu, Yu-Ming Lin, Jen-Yu Wang
  • Patent number: 9722093
    Abstract: An oxide semiconductor transistor includes an oxide semiconductor channel layer, a metal gate, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The metal gate is disposed on the oxide semiconductor channel layer. The gate insulation layer is disposed between the metal gate and the oxide semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the metal gate. The ferroelectric material layer is disposed between the internal electrode and the metal gate. The ferroelectric material layer in the oxide semiconductor transistor of the present invention is used to enhance the electrical characteristics of the oxide semiconductor transistor.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: August 1, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Su Xing, Hsueh-Wen Wang, Chien-Yu Ko, Yu-Cheng Tung, Jen-Yu Wang, Cheng-Tung Huang, Yu-Ming Lin
  • Patent number: 9632115
    Abstract: A method for deriving characteristic values of a MOS transistor is described. A set of ?k values is provided. A set of VBi values (i=1 to M, M?3) is provided. A set of RSDi,j (i=1 to M?1, j=i+1 to M) values each under a pair of VBi and VBj, or a set of Vtq_q,j (q is one of 1 to M, j is 1 to M excluding q) values under VBq is derived for each ?k, with an iteration method. The ?k value making the set of RSDi,j values or Vtq_q,j values closest to each other is determined as an accurate ?k value. The mean value of RSDi,j at the accurate ?k value is calculated as an accurate RSD value.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: April 25, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Ting Wu, Cheng-Tung Huang, Tsung-Han Lee, Yi-Han Ye
  • Publication number: 20170040346
    Abstract: A method for fabricating substrate of a semiconductor device includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.
    Type: Application
    Filed: October 17, 2016
    Publication date: February 9, 2017
    Inventors: Wen-Yin Weng, Cheng-Tung Huang, Ya-Ru Yang, Yi-Ting Wu, Yu-Ming Lin, Jen-Yu Wang
  • Patent number: 9508799
    Abstract: A method for fabricating substrate of a semiconductor device is disclosed. The method includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: November 29, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Yin Weng, Cheng-Tung Huang, Ya-Ru Yang, Yi-Ting Wu, Yu-Ming Lin, Jen-Yu Wang
  • Publication number: 20160228240
    Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems used to deliver a prosthetic heart valve to a deficient valve. In one embodiment, for instance, a support structure and an expandable prosthetic valve are advanced through the aortic arch of a patient using a delivery system. The support structure is delivered to a position on or adjacent to the surface of the outflow side of the aortic valve (the support structure defining a support-structure interior). The expandable prosthetic valve is delivered into the aortic valve and into the support-structure interior. The expandable prosthetic heart valve is expanded while the expandable prosthetic heart valve is in the support-structure interior and while the support structure is at the position on or adjacent to the surface of the outflow side of the aortic valve, thereby causing one or more native leaflets of the aortic valve to be frictionally secured between the support structure and the expanded prosthetic heart valve.
    Type: Application
    Filed: April 15, 2016
    Publication date: August 11, 2016
    Inventors: Christopher J. Olson, Glen Thomas Rabito, Dustin P. Armer, Minh T. Ma, Devin H. Marr, Cheng-Tung Huang, Hiroshi Okabe, Kevin M. Stewart, Alison S. Curtis, Philip P. Corso, JR.
  • Publication number: 20160141288
    Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.
    Type: Application
    Filed: November 13, 2014
    Publication date: May 19, 2016
    Inventors: Wen-Yin Weng, Cheng-Tung Huang, Wei-Heng Hsu, Yu-Ming Lin, Ya-Ru Yang
  • Patent number: 9299839
    Abstract: A P-type field effect transistor includes: a gate area; an insulated area, adjacent to the gate area; a source region and a drain region made by silicon germanium, respectively, adjacent to the second side of the insulated area; a channel area, adjacent to the insulated area and formed between the source region and the drain region; a conductive layer, electrically connected to the source region and the drain region, respectively; and a plurality of capping layers, connected between the conductive layer and the source/drain regions, wherein the silicon layer(s) and the silicon germanium layer(s) are stacked alternately, and of which a silicon layer contacts the source/drain silicon germanium regions, while a silicon germanium layer contacts the conductive layer. The present invention also provides a complementary metal oxide semiconductor transistor including the P-type field effect transistor mentioned above.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: March 29, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Wen-Yin Weng, Cheng-Tung Huang, Wei-Heng Hsu, Yi-Ting Wu, Yu-Ming Lin, Jen-Yu Wang
  • Publication number: 20160064563
    Abstract: A P-type field effect transistor includes: a gate area; an insulated area, adjacent to the gate area; a source region and a drain region made by silicon germanium, respectively, adjacent to the second side of the insulated area; a channel area, adjacent to the insulated area and formed between the source region and the drain region; a conductive layer, electrically connected to the source region and the drain region, respectively; and a plurality of capping layers, connected between the conductive layer and the source/drain regions, wherein the silicon layer(s) and the silicon germanium layer(s) are stacked alternately, and of which a silicon layer contacts the source/drain silicon germanium regions, while a silicon germanium layer contacts the conductive layer. The present invention also provides a complementary metal oxide semiconductor transistor including the P-type field effect transistor mentioned above.
    Type: Application
    Filed: October 3, 2014
    Publication date: March 3, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: WEN-YIN WENG, CHENG-TUNG HUANG, WEI-HENG HSU, YI-TING WU, YU-MING LIN, JEN-YU WANG
  • Publication number: 20160064485
    Abstract: A method for fabricating substrate of a semiconductor device is disclosed. The method includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.
    Type: Application
    Filed: August 26, 2014
    Publication date: March 3, 2016
    Inventors: Wen-Yin Weng, Cheng-Tung Huang, Ya-Ru Yang, Yi-Ting Wu, Yu-Ming Lin, Jen-Yu Wang
  • Publication number: 20160003888
    Abstract: A method of characterizing a device may be used to determine a metal work function of the device according to a threshold voltage, a body effect, and an oxide capacitance of the device. The threshold voltage may be determined according to a current to voltage curve. The oxide capacitance may be determined according to a capacitor to voltage curve.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Inventors: Wen-Yin Weng, Wei-Heng Hsu, Cheng-Tung Huang, Yi-Ting Wu, Yu-Ming Lin, Jen-Yu Wang