Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems used to deliver a prosthetic heart valve to a deficient valve. In one embodiment, for instance, a support structure and an expandable prosthetic valve are advanced through the aortic arch of a patient using a delivery system. The support structure is delivered to a position on or adjacent to the surface of the outflow side of the aortic valve (the support structure defining a support-structure interior). The expandable prosthetic valve is delivered into the aortic valve and into the support-structure interior. The expandable prosthetic heart valve is expanded while the expandable prosthetic heart valve is in the support-structure interior and while the support structure is at the position on or adjacent to the surface of the outflow side of the aortic valve, thereby causing one or more native leaflets of the aortic valve to be frictionally secured between the support structure and the expanded prosthetic heart valve.

Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.

Abstract: A P-type field effect transistor includes: a gate area; an insulated area, adjacent to the gate area; a source region and a drain region made by silicon germanium, respectively, adjacent to the second side of the insulated area; a channel area, adjacent to the insulated area and formed between the source region and the drain region; a conductive layer, electrically connected to the source region and the drain region, respectively; and a plurality of capping layers, connected between the conductive layer and the source/drain regions, wherein the silicon layer(s) and the silicon germanium layer(s) are stacked alternately, and of which a silicon layer contacts the source/drain silicon germanium regions, while a silicon germanium layer contacts the conductive layer. The present invention also provides a complementary metal oxide semiconductor transistor including the P-type field effect transistor mentioned above.

Abstract: A method for fabricating substrate of a semiconductor device is disclosed. The method includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.

Abstract: A P-type field effect transistor includes: a gate area; an insulated area, adjacent to the gate area; a source region and a drain region made by silicon germanium, respectively, adjacent to the second side of the insulated area; a channel area, adjacent to the insulated area and formed between the source region and the drain region; a conductive layer, electrically connected to the source region and the drain region, respectively; and a plurality of capping layers, connected between the conductive layer and the source/drain regions, wherein the silicon layer(s) and the silicon germanium layer(s) are stacked alternately, and of which a silicon layer contacts the source/drain silicon germanium regions, while a silicon germanium layer contacts the conductive layer. The present invention also provides a complementary metal oxide semiconductor transistor including the P-type field effect transistor mentioned above.

Abstract: A method of characterizing a device may be used to determine a metal work function of the device according to a threshold voltage, a body effect, and an oxide capacitance of the device. The threshold voltage may be determined according to a current to voltage curve. The oxide capacitance may be determined according to a capacitor to voltage curve.

Abstract: A method for deriving characteristic values of a MOS transistor is described. A set of ?k values is provided. A set of VBi values (i=1 to M, M?3) is provided. A set of RSDi,j (i=1 to M?1, j=i+1 to M) values each under a pair of VBi and VBj, or a set of Vtq—q,j (q is one of 1 to M, j is 1 to M excluding q) values under VBq is derived for each ?k, with an iteration method. The ?k value making the set of RSDi,j values or Vtq—q,j values closest to each other is determined as an accurate ?k value. The mean value of RSDi,j at the accurate ?k value is calculated as an accurate RSD value.

Abstract: Provided is a method of fabricating a MOS device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer. A first implant process is performed to form source and drain extension regions in the substrate, wherein the gate conductive layer is covered by the hard mask layer. A process is of removing the hard mask layer is performed to expose the surface of the gate conductive layer. A second implant process is performed to form pocket doped regions in the substrate, wherein the gate conductive layer is not covered by the hard mask layer.

Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.

Abstract: Provided is a method of fabricating a MOS device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer. A first implant process is performed to form source and drain extension regions in the substrate, wherein the gate conductive layer is covered by the hard mask layer. A process is of removing the hard mask layer is performed to expose the surface of the gate conductive layer. A second implant process is performed to form pocket doped regions in the substrate, wherein the gate conductive layer is not covered by the hard mask layer.

Abstract: A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.

Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.

Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.

Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.

Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.

Abstract: A method for forming a metal-oxide-semiconductor (MOS) device includes at least steps of forming a pair of trenches in a substrate at both sides of a gate structure, filling the trenches with a silicon germanium layer by a selective epitaxy growth process, forming a cap layer on the silicon germanium layer by a selective growth process, and forming a pair of source/drain regions by performing an ion implantation process. Hence, the undesirable effects caused by ion implantation can be mitigated.

Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.

Abstract: A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.

Abstract: A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device. The testkey design patterns are advantageous in measuring capacitance with less error and for better gate oxide thickness extraction.

Abstract: An exemplary semiconductor device includes a substrate, a spacer, a metal silicide layer and carbon atoms. The substrate has a gate structure formed thereon. The spacer is formed on the sidewall of the gate structure. The spacer has a first side adjacent to the gate structure and a second side away from the gate structure. The metal silicide layer is formed on the substrate and adjacent to the second side of the spacer but away from the first side of the spacer. The carbon atoms are formed into the substrate and adjacent to the first side of the spacer but away from the second side of the spacer.