Patents by Inventor Cheng-Tung Huang

Cheng-Tung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7888194
    Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: February 15, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Li-Shian Jeng, Cheng-Tung Huang, Shyh-Fann Ting, Wen-Han Hung, Kun-Hsien Lee, Meng-Yi Wu, Tzyy-Ming Cheng
  • Patent number: 7888223
    Abstract: A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: February 15, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Meng-Yi Wu, Tzyy-Ming Cheng
  • Patent number: 7875520
    Abstract: A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is performed to form a lightly doped drain (LDD) in the second active area after an epitaxial layer is formed in the first active area. On the other hand, the ion implantation process is performed to form the respective LDD of the first active area and the second active area. After the epitaxial layer in the first active area is formed, another ion implantation process is performed to implant dopants into the LDD of the second active area again.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: January 25, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Meng-Yi Wu, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Kun-Hsien Lee, Li-Shian Jeng, Shih-Jung Tu, Yu-Ming Lin, Yao-Chin Cheng
  • Publication number: 20110012197
    Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 20, 2011
    Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
  • Patent number: 7749833
    Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: July 6, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Wen-Han Hung, Tzyy-Ming Cheng, Tzer-Min Shen, Yi-Chung Sheng
  • Patent number: 7700450
    Abstract: A method for forming a MOS transistor includes providing a substrate having at least a gate structure formed thereon, performing a pre-amorphization (PAI) process to form amorphized regions in the substrate, sequentially performing a co-implantation process, a first ion implantation process, and a first rapid thermal annealing (RTA) process to form lightly doped drains (LDDs), forming spacers on sidewalls of the gate structure, and forming a source/drain.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: April 20, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Shyh-Fann Ting, Wen-Han Hung, Li-Shian Jeng, Tzyy-Ming Cheng
  • Patent number: 7682890
    Abstract: A method of fabricating a semiconductor device is provided. A substrate is first provided, and then several IO devices and several core devices are formed on the substrate, wherein those IO devices include IO PMOS and IO NMOS, and those core devices include core PMOS and core NMOS. Thereafter, a buffer layer is formed on the substrate, and then the buffer layer except a surface of the IO PMOS is removed in order to reduce the negative bias temperature instability (NBTI) of the IO PMOS. Afterwards, a tensile contact etching stop layer (CESL) is formed on the IO NMOS and the core NMOS, and a compressive CESL is formed the core PMOS.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: March 23, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Han Hung, Cheng-Tung Huang, Li-Shian Jeng, Kun-Hsien Lee, Shyh-Fann Ting, Tzyy-Ming Cheng, Chia-Wen Liang
  • Patent number: 7642166
    Abstract: A method of manufacturing a MOS transistor device is provided. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: January 5, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Neng-Kuo Chen, Shao-Ta Hsu, Teng-Chun Tsai, Chien-Chung Huang
  • Patent number: 7622344
    Abstract: A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: November 24, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Wen Liang, Cheng-Tung Huang, Shyh-Fann Ting, Chih-Chiang Wu, Shih-Chieh Hsu, Li-Shian Jeng, Kun-Hsien Lee, Meng-Yi Wu, Wen-Han Hung, Tzyy-Ming Cheng
  • Patent number: 7618856
    Abstract: A semiconductor substrate having a first active region and a second active region for fabricating a first transistor and a second transistor is provided. A first gate structure and a second gate structure are formed on the first active region and the second active region and a first spacer is formed surrounding the first gate structure and the second gate structure. A source/drain region for the first transistor and the second transistor is formed. The first spacer is removed from the first gate structure and the second gate structure and a cap layer is disposed on the first transistor and the second transistor and the cap layer covering the second transistor is removed thereafter. An etching process is performed to form a recess in the substrate surrounding the second gate structure. An epitaxial layer is formed in the recess and the cap layer is removed from the first transistor.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: November 17, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Jing-Chang Wu, Kun-Hsien Lee, Wen-Han Hung, Li-Shian Jeng, Tzer-Min Shen, Tzyy-Ming Cheng, Nien-Chung Li
  • Publication number: 20090246922
    Abstract: A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is performed to form a lightly doped drain (LDD) in the second active area after an epitaxial layer is formed in the first active area. On the other hand, the ion implantation process is performed to form the respective LDD of the first active area and the second active area. After the epitaxial layer in the first active area is formed, another ion implantation process is performed to implant dopants into the LDD of the second active area again.
    Type: Application
    Filed: March 27, 2008
    Publication date: October 1, 2009
    Inventors: Meng-Yi Wu, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Kun-Hsien Lee, Li-Shian Jeng, Shih-Jung Tu, Yu-Ming Lin, Yao-Chin Cheng
  • Publication number: 20090239347
    Abstract: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device. The method includes at least the steps of forming a silicon germanium layer by the selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the selective growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.
    Type: Application
    Filed: May 20, 2009
    Publication date: September 24, 2009
    Applicant: United Microelectronics Corp.
    Inventors: SHYH-FANN TING, Shih-Chieh Hsu, Cheng-Tung Huang, Chih-Chiang Wu, Wen-Han Hung, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Kun-Hsien Lee, Tzyy-Ming Cheng
  • Publication number: 20090224328
    Abstract: A semiconductor device includes a substrate defining an active area thereon, a shallow trench isolation on the substrate and directly surrounding the active area, a gate, a source and a drain on the active area and a hard mask on the border of the shallow trench isolation and the active area.
    Type: Application
    Filed: March 4, 2008
    Publication date: September 10, 2009
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Wen-Han Hung, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Tzyy-Ming Cheng, Jing-Chang Wu, Tzer-Min Shen
  • Patent number: 7585790
    Abstract: A method of forming a semiconductor device. The method comprises steps of providing a substrate having a first transistor, a second transistor and non-salicide device formed thereon and the conductive type of the first transistor is different from that of the second transistor. A buffer layer is formed over the substrate and a tensile material layer is formed over the buffer layer. A portion of the tensile material layer over the second transistor is thinned and a spike annealing process is performed. The tensile material layer is removed to expose the buffer layer over the substrate and a patterned salicide blocking layer is formed over the non-salicide device. A salicide process is performed for forming a salicide layer on a portion of the first transistor and the second transistor.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: September 8, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Han Hung, Cheng-Tung Huang, Kun-Hsien Lee, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Chia-Wen Liang, Neng-Kuo Chen
  • Patent number: 7582520
    Abstract: A method of fabricating a metal-oxide-semiconductor transistor is provided. A first gate structure and a second gate structure are formed on a substrate. The first gate structure has a dimension greater than the second gate structure. Then, first lightly doped drain regions are formed in the substrate on two sides of the first gate structure. A lightly doped drain annealing process is performed. Next, second lightly doped drain regions are formed in the substrate on two sides of the second gate structure. First spacers are formed on the sidewalls of the first gate structure and second spacers are formed on the sidewalls of the second gate structure at the same time. Afterwards, first source/drain regions are formed in the substrate on two sides of the first spacers and second source/drain regions are formed in the substrate on two sides of the second spacers. A source/drain annealing process is performed.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: September 1, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Li-Shian Jeng, Wen-Han Hung, Shyh-Fann Ting, Jing-Yi Huang, Tzyy-Ming Cheng, Chia-Wen Liang
  • Publication number: 20090186475
    Abstract: A method of manufacturing a MOS transistor, in which, a tri-layer photo resist layer is used to form a patterned hard mask layer having a sound shape and a small size, and the patterned hard mask layer is used to form a gate. Thereafter, by forming and defining a cap layer, a recess is formed through etching in the substrate. The patterned hard mask is removed after epitaxial layers are formed in the recesses. Accordingly, a conventional poly bump issue and an STI oxide loss issue leading to contact bridge can be avoided.
    Type: Application
    Filed: January 21, 2008
    Publication date: July 23, 2009
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Shih-Chieh Hsu, Chih-Chiang Wu, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Kun-Hsien Lee, Wen-Han Hung, Yao-Chin Cheng, Chi-Sheng Tseng, Yu-Ming Lin, Shih-Jung Tu, Tzyy-Ming Cheng
  • Publication number: 20090166625
    Abstract: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 2, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shyh-Fann Ting, Shih-Chieh Hsu, Cheng-Tung Huang, Chih-Chiang Wu, Wen-Han Hung, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Kun-Hsien Lee, Tzyy-Ming Cheng
  • Patent number: 7550356
    Abstract: A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region; performing a first rapid thermal annealing (RTA) process; removing the spacer and forming a high tensile stress film over the surface of the gate and the source/drain region; and performing a second rapid thermal annealing process.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: June 23, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Tung Huang, Chia-Wen Liang, Tzyy-Ming Cheng, Tzer-Min Shen, Yi-Chung Sheng
  • Publication number: 20090137089
    Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.
    Type: Application
    Filed: February 5, 2009
    Publication date: May 28, 2009
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Wen-Han Hung, Tzyy-Ming Cheng, Tzer-Min Shen, Yi-Chung Sheng
  • Publication number: 20090117701
    Abstract: A method for manufacturing a MOS transistor includes performing a thermal treatment to repair damaged substrate before forming source/drain extension regions, accordingly negative bias temperature instability (NBTI) is reduced. Since the thermal treatment is performed before forming the source/drain extension regions, heat budget for forming the source/drain extension regions and junction depth and junction profile of the source/drain extension would not be affected. Therefore the provided method for manufacturing a MOS transistor is capable of reducing short channel effect and possesses a superior process compatibility.
    Type: Application
    Filed: November 1, 2007
    Publication date: May 7, 2009
    Inventors: Meng-Yi Wu, Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Chung-Min Shih, Yao-Chin Cheng, Tzyy-Ming Cheng