Abstract: A method for modulating a threshold voltage of a device. The method includes providing a fin extending from a substrate, where the fin includes a plurality of semiconductor channel layers defining a channel region for a P-type transistor. In some embodiments, the method further includes forming a first gate dielectric layer surrounding at least three sides of each of the plurality of semiconductor channel layers of the P-type transistor. Thereafter, the method further includes forming a P-type metal film surrounding the first gate dielectric layer. In an example, and after forming the P-type metal film, the method further includes annealing the semiconductor device. After the annealing, and in some embodiments, the method includes removing the P-type metal film.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a buffer layer, a barrier layer, a dielectric layer, a source structure, and a drain structure. The buffer layer is disposed on the substrate. The barrier layer is disposed on the buffer layer. The dielectric layer is disposed on the barrier layer. The passivation layer is disposed on the dielectric layer. The source structure and the drain structure are disposed on the passivation layer.

Abstract: Embodiments of the present disclosure provide a method of forming a contact opening using selective ALE operations to remove ILD layer along an upper profile of a source/drain region, and then form a source/drain contact feature having a concave bottom profile with increased contact area.

Abstract: A semiconductor structure includes a substrate, a gate structure on the substrate, and a source structure and a drain structure on opposite sides of the gate structure. The gate structure includes a gate electrode on the substrate and a gate metal layer on the gate electrode. The gate metal layer has at least one notch, which exposes the gate electrode below. The electric potential of the source structure is different from that of the gate structure.

Abstract: A method for forming a high electron mobility transistor (HEMT) includes forming a buffer layer on a transparent substrate. The method further includes forming a barrier layer on the buffer layer. A channel region is formed in the buffer layer adjacent to the interface between the buffer layer and the barrier layer. The method further includes forming a dielectric layer on the barrier layer. The method further includes forming source/drain electrodes through the dielectric layer and the barrier layer and disposed on the buffer layer. The method further includes forming a shielding layer conformally covering the dielectric layer and the source/drain electrodes. The method further includes performing a thermal process on the source/drain electrodes.

Abstract: An input method applied to a foldable electronic apparatus with pivotally connected first and second bodies is provided. The first body includes a display and a first G sensor. The second body includes a touch input portion and a second G sensor. First and second Euler angles of the first and second bodies are respectively detected by the first and second G sensors. A placement state of the foldable electronic apparatus is determined according to the first and second Euler angles. When the placement state is determined as a landscape state, the display displays a horizontal frame, and an input signal is executed according to the horizontal frame. When the placement state is converted to a portrait state, the horizontal frame is rotated to a portrait frame, the input signal is executed according to the portrait frame, and vertical and horizontal coordinates of the touch input portion are swapped.

Abstract: An input method applied to a foldable electronic apparatus with pivotally connected first and second bodies is provided. The first body includes a display and a first G sensor. The second body includes a touch input portion and a second G sensor. First and second Euler angles of the first and second bodies are respectively detected by the first and second G sensors. A placement state of the foldable electronic apparatus is determined according to the first and second Euler angles. When the placement state is determined as a landscape state, the display displays a horizontal frame, and an input signal is executed according to the horizontal frame. When the placement state is converted to a portrait state, the horizontal frame is rotated to a portrait frame, the input signal is executed according to the portrait frame, and vertical and horizontal coordinates of the touch input portion are swapped.

Abstract: A method of forming a semiconductor device includes: providing a substrate, wherein a buffer layer, a channel layer, and a barrier layer are sequentially formed on the substrate; forming a doped compound semiconductor layer on a portion of the barrier layer; forming a first etch stop layer on the doped compound semiconductor layer; forming a second etch stop layer on the first etch stop layer; forming a first dielectric layer on the second etch stop layer; forming an etch protection layer on the first dielectric layer; performing a first etch process to form a recess in the first dielectric layer; performing a second etch process to form an opening exposing a portion of the second etch stop layer; performing a removal process to remove remaining portions of the etch protection layer on the first dielectric layer; and forming a gate metal layer to fill the opening.

Abstract: A method of forming a semiconductor device includes: providing a substrate, wherein a buffer layer, a channel layer, and a barrier layer are sequentially formed on the substrate; forming a doped compound semiconductor layer on a portion of the barrier layer; forming a first etch stop layer on the doped compound semiconductor layer; forming a second etch stop layer on the first etch stop layer; forming a first dielectric layer on the second etch stop layer; forming an etch protection layer on the first dielectric layer; performing a first etch process to form a recess in the first dielectric layer; performing a second etch process to form an opening exposing a portion of the second etch stop layer; performing a removal process to remove remaining portions of the etch protection layer on the first dielectric layer; and forming a gate metal layer to fill the opening.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate; a source structure and a drain structure disposed on the substrate; a gate structure disposed on the substrate and between the source structure and the drain structure; a first field plate disposed on the substrate; a first oxide layer disposed between the substrate and the first field plate; a second field plate disposed on the first field plate, wherein the second field plate is closer to the drain structure than the first field plate; a planarized second oxide layer disposed between the first oxide layer and the second field plate; and a third field plate disposed on the second field plate, wherein the third field plate is closer to the drain structure than the second field plate.

Abstract: A semiconductor structure includes a substrate, a gate structure on the substrate, and a source structure and a drain structure on opposite sides of the gate structure. The gate structure includes a gate electrode on the substrate and a gate metal layer on the gate electrode. The gate metal layer has at least one notch, which exposes the gate electrode below. The electric potential of the source structure is different from that of the gate structure.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a buffer layer, a barrier layer, a dielectric layer, a source structure, and a drain structure. The buffer layer is disposed on the substrate. The barrier layer is disposed on the buffer layer. The dielectric layer is disposed on the barrier layer. The passivation layer is disposed on the dielectric layer. The source structure and the drain structure are disposed on the passivation layer.

Abstract: A semiconductor structure and a method for forming the same are provided. A semiconductor structure includes a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, a first transistor on the epitaxial layer, an interlayer dielectric layer on the epitaxial layer, a dielectric pillar penetrating through the interlayer dielectric layer and the epitaxial layer, and a conductive liner disposed on a sidewall of the dielectric pillar. The conductive liner is electrically connected to the first transistor and the seed layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate; a source structure and a drain structure disposed on the substrate; a gate structure disposed on the substrate and between the source structure and the drain structure; a first field plate disposed on the substrate; a first oxide layer disposed between the substrate and the first field plate; a second field plate disposed on the first field plate, wherein the second field plate is closer to the drain structure than the first field plate; a planarized second oxide layer disposed between the first oxide layer and the second field plate; and a third field plate disposed on the second field plate, wherein the third field plate is closer to the drain structure than the second field plate.

Abstract: A semiconductor device includes a first composite III-V group compound semiconductor layer disposed on a composite substrate, and a second III-V group compound semiconductor layer disposed on the first composite III-V group compound semiconductor layer. The semiconductor device also includes a gate structure disposed on the second III-V group compound semiconductor layer, and a source electrode and a drain electrode disposed on the second III-V group compound semiconductor layer and at opposite sides of the gate structure. The semiconductor device further includes a field plate disposed between the gate structure and the drain electrode, and a conductive structure penetrating through the second III-V group compound semiconductor layer and the first composite III-V group compound semiconductor layer, wherein the field plate is electrically connected to the composite substrate through the conductive structure.

Abstract: A method for forming a high electron mobility transistor (HEMT) includes forming a buffer layer on a transparent substrate. The method further includes forming a barrier layer on the buffer layer. A channel region is formed in the buffer layer adjacent to the interface between the buffer layer and the barrier layer. The method further includes forming a dielectric layer on the barrier layer. The method further includes forming source/drain electrodes through the dielectric layer and the barrier layer and disposed on the buffer layer. The method further includes forming a shielding layer conformally covering the dielectric layer and the source/drain electrodes. The method further includes performing a thermal process on the source/drain electrodes.

Abstract: A semiconductor device includes a first composite III-V group compound semiconductor layer disposed on a composite substrate, and a second III-V group compound semiconductor layer disposed on the first composite III-V group compound semiconductor layer. The semiconductor device also includes a gate structure disposed on the second III-V group compound semiconductor layer, and a source electrode and a drain electrode disposed on the second III-V group compound semiconductor layer and at opposite sides of the gate structure. The semiconductor device further includes a field plate disposed between the gate structure and the drain electrode, and a conductive structure penetrating through the second III-V group compound semiconductor layer and the first composite III-V group compound semiconductor layer, wherein the field plate is electrically connected to the composite substrate through the conductive structure.

Abstract: A method for forming a high electron mobility transistor (HEMT) includes forming a buffer layer on a transparent substrate. The method further includes forming a barrier layer on the buffer layer. A channel region is formed in the buffer layer adjacent to the interface between the buffer layer and the barrier layer. The method further includes forming a dielectric layer on the barrier layer. The method further includes forming source/drain electrodes through the dielectric layer and the barrier layer and disposed on the buffer layer. The method further includes forming a shielding layer conformally covering the dielectric layer and the source/drain electrodes. The method further includes performing a thermal process on the source/drain electrodes.

Abstract: A mounting assembly and an inverter assembly using the same are disclosed. The mounting assembly includes a waterproof component and a fixing component. The waterproof component includes a first side facing the inverter, a second side facing the wall surface, an opening and a gasket set. The opening runs through the first side and the second side. The gasket set is disposed around the opening. The gasket set abuts against the wall surface and the inverter. The inverter is electrically connected with a wire running through the opening. The fixing component is disposed on the wall surface and connected to the waterproof component. The fixing component includes a third surface facing the inverter, a fourth surface facing the wall surface, and a first engaging element. The first engaging element engages with a second engaging element of the inverter to mount the inverter on the wall surface.