Patents by Inventor Cheng-Wei Huang

Cheng-Wei Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8295558
    Abstract: An image previewing system includes a display unit, a face portion recognition unit, a selecting unit, a comparing unit and a magnifying unit. The display unit comprises a screen configured to show an image. The face portion recognition unit is configured to recognize any human face contained in the image and determine face portions in the image if human face(s) exists in the image. The selecting unit is configured to select one of the face portions in the image. The comparing unit is configured to compare the number of image pixels of the selected face portion with the resolution of the screen of the display unit and generate a result. According to the result, the magnifying unit configured to magnify the selected face portion and display the magnified face portion on the screen.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: October 23, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Yu-Tsung Su, Cheng-Wei Huang
  • Patent number: 8274581
    Abstract: An image capture device includes an image capture unit, a switching unit, a calculation unit, a comparison unit, and a display unit. The image capture unit captures consecutive images. The switching unit switches to a playback mode. The calculation unit calculates each of gradient values between adjacent pixels within each the image and cumulates a total value composed of the gradient values of the image. The comparison unit compares different total values corresponding to different images to determine the image having a maximum total value. The display unit displays the acquired image.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: September 25, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Yu-Tsung Su, Cheng-Wei Huang
  • Patent number: 8250393
    Abstract: A power management method for use in a computer system having a processor, a power management module and a phase lock loop circuit (PLL) is provided. The power management module is coupled to a plurality of peripheral modules and the computer system and the processor are capable of being operated in a working state and power saving states. The method includes the following. When the computer system is operated in the working state and the processor is entered into a lowest power consumption state among the power saving states, states of the peripheral modules are detected to determine whether a specific condition has been matched. If the specific condition is matched, the processor is directed to a control state to control the PLL according to a control state configuration.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: August 21, 2012
    Assignee: Via Technologies, Inc.
    Inventors: Shuang-Shuang Qin, Cheng-Wei Huang
  • Publication number: 20120158275
    Abstract: The disclosure provides a real-time traffic situation awareness system. In one embodiment, the real-time traffic situation awareness system receives driving data from a car, wherein the driving data comprises an image, GPS data, and gyroscope sensor data. The real-time traffic situation awareness system comprises an image processing unit, a feature extraction unit, a feature matrix database, a data grouping unit, and a situation awareness unit. The image processing unit processes the image to generate a processed image. The feature extraction unit generates a data point according to the processed image, the GPS data, and the gyroscope sensor data. The data grouping unit searches the feature matrix database for a plurality of feature groups of an optimal feature matrix corresponding to a geographic area according to the GPS data of the data point. The situation awareness unit analyzes the feature groups to generate traffic information.
    Type: Application
    Filed: June 23, 2011
    Publication date: June 21, 2012
    Inventors: Cheng-Wei Huang, Shyi-Shing Hsieh
  • Patent number: 8110931
    Abstract: A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: February 7, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsiao Chuan Chang, Tsung Yueh Tsai, Yi Shao Lai, Ho Ming Tong, Jian Cheng Chen, Wei Chi Yih, Chang Ying Hung, Cheng Wei Huang, Chih Hsing Chen, Tai Yuan Huang, Chieh Ting Chen, Yi Tsai Lu
  • Patent number: 8065547
    Abstract: Provided is a control method for an advanced configuration and power interface (ACPI) in a computer system. The computer system comprises a processor and a bus master, wherein the processor, as defined by the ACPI specification, has a first state (C0 state), a second state (C1 state), a third state (C2 state), a fourth state (C3 state) and a fifth state (C4 state). The method comprises enabling the processor to run in the C2 state when a request from the bus master is issued before the processor enters the C3 state, or enables the processor to ignore the C4 state and complete the C3 state when the request from the bus master is issued at the C3 state and before entering the C4 state.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: November 22, 2011
    Assignee: Via Technologies, Inc.
    Inventors: Jen-Po Chang, Grace Qin, Cheng-Wei Huang, Ying-Chung Chen
  • Patent number: 7955897
    Abstract: A chip structure according to the present invention is provided. A plurality of pedestals extends from the back surface of the chip structure. Each of the pedestals is located at a position away from the edge of the back surface for a non-zero distance so that the pedestals of an upper chip structure will not damage the bonding pads positioned on the edge of the active surface of a lower chip structure when the upper chip structure is stacked on the active surface of the lower chip structure with the pedestals.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: June 7, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung Yueh Tsai, Yi Shao Lai, Cheng Wei Huang
  • Patent number: 7958383
    Abstract: A computer system has an adjustable data transmission rate between a CPU and a core logic chip thereof. In the computer system, the CPU has a power state adjustable in response to a power management control signal issued by the core logic chip. For adjusting data transmission rate between the CPU and the core logic chip, a change of an asserted time of the power management control signal from a first time period to a second time period is first determined to obtain an index value. The data transmission rate is increased or decreased according to the index value.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: June 7, 2011
    Assignee: Via Technologies, Inc.
    Inventors: Chien-Ping Chung, Cheng-Wei Huang, Chi Chang
  • Patent number: 7949244
    Abstract: An exemplary method for measuring a distance from a subject to a camera includes the following operations: focusing on the subject using the imaging system; illuminating an area on the subject using auxiliary light; capturing an image of the subject, the image having an illumination portion corresponding to the illuminated area; measuring the area of the illumination portion of the image; and calculating the subject distance based on the measured area.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: May 24, 2011
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Cheng-Wei Huang
  • Publication number: 20100281277
    Abstract: A stand-by mode management module applied in a computer system having a BIOS (basic input/output system), a graphic module and a display module is provided. The computer system is operated in a working state and at least one stand-by state. The module includes a timer and an interrupt generation unit. The timer starts a count period when detecting that the computer system is idle. The interrupt generation unit generates an interrupt request to the BIOS to request the computer system to prepare to enter to a specific state when the count period is reached. When the specific state is entered, the computer system enters the stand-by state, a PLL (phase lock loop) of the display module keeps turning on, and PLLs other than the PLL of the display module are turned off and the graphic module acquires a frame stored in a fixed area of a storing unit and displays the acquired frame on the display module.
    Type: Application
    Filed: November 17, 2009
    Publication date: November 4, 2010
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Shuang-Shuang Qin, Cheng-Wei Huang
  • Publication number: 20100272368
    Abstract: An image previewing system includes a display unit, a face portion recognition unit, a selecting unit, a comparing unit and a magnifying unit. The display unit comprises a screen configured to show an image. The face portion recognition unit is configured to recognize any human face contained in the image and determine face portions in the image if human face(s) exists in the image. The selecting unit is configured to select one of the face portions in the image. The comparing unit is configured to compare the number of image pixels of the selected face portion with the resolution of the screen of the display unit and generate a result. According to the result, the magnifying unit configured to magnify the selected face portion and display the magnified face portion on the screen.
    Type: Application
    Filed: August 5, 2009
    Publication date: October 28, 2010
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YU-TSUNG SU, CHENG-WEI HUANG
  • Publication number: 20100275045
    Abstract: A power management method for use in a computer system having a processor, a power management module and a phase lock loop circuit (PLL) is provided. The power management module is coupled to a plurality of peripheral modules and the computer system and the processor are capable of being operated in a working state and power saving states. The method includes the following. When the computer system is operated in the working state and the processor is entered into a lowest power consumption state among the power saving states, states of the peripheral modules are detected to determine whether a specific condition has been matched. If the specific condition is matched, the processor is directed to a control state to control the PLL according to a control state configuration.
    Type: Application
    Filed: November 23, 2009
    Publication date: October 28, 2010
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Shuang-Shuang Qin, Cheng-Wei Huang
  • Publication number: 20100259640
    Abstract: An image capture device includes an image capture unit, a switching unit, a calculation unit, a comparison unit, and a display unit. The image capture unit captures consecutive images. The switching unit switches to a playback mode. The calculation unit calculates each of gradient values between adjacent pixels within each the image and cumulates a total value composed of the gradient values of the image. The comparison unit compares different total values corresponding to different images to determine the image having a maximum total value. The display unit displays the acquired image.
    Type: Application
    Filed: August 27, 2009
    Publication date: October 14, 2010
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YU-TSUNG SU, CHENG-WEI HUANG
  • Patent number: 7774629
    Abstract: A method for power management of a CPU and a system thereof, which drive the CPU to enter a more efficient power saving state are disclosed. A chip of the present invention sends a first control signal to drive the CPU to wake from a non-snooping sleep state and enter a normally executing instruction state as well as a system management mode to execute a system management interrupt routine. Then the chip enables an arbiter to transmit a bus master request to the CPU for processing. After completing the processing of the bus master request, the chip disables the arbiter and the CPU drives the chip to send a second control signal to drive the CPU to return to the non-snooping sleep state according the system management interrupt routine.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: August 10, 2010
    Assignee: Via Technologies, Inc.
    Inventors: Wen-Juin Huang, Chung-Chin Huang, Cheng-Wei Huang, Jui-Ming Wei
  • Publication number: 20100097543
    Abstract: A liquid crystal display structure is provided. The liquid crystal display structure includes a liquid crystal panel and a backlight module. The liquid crystal panel has a liquid crystal layer including photo-polymerizable monomers. The backlight module has a light emitting unit for emitting an output light. A difference between the smallest value of the spectrum interval of the output light and the largest value of the absorption spectrum interval of the photo-polymerizable monomer in the liquid crystal layer is larger than or equal to 40 nm.
    Type: Application
    Filed: September 16, 2009
    Publication date: April 22, 2010
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Chih-Ho Chiu, Te-Sheng Chen, Chung-Ching Hsieh, Chia-Hsuan Pai, Cheng-Wei Huang, Sugiura Norio
  • Publication number: 20100053527
    Abstract: A method for manufacturing a liquid crystal display (LCD) panel is provided. The method comprises the following steps. Firstly, an upper substrate and a lower substrate are provided. Next, a liquid crystal material is interposed between the upper and lower substrates. The liquid crystal material comprises at least one liquid crystal molecule and at least two photosensitive monomers, and the absorption peak of at least one photosensitive monomer is larger than 300 nm. Then, a voltage is applied between the upper substrate and the lower substrate, and a ultra-violet with a first wavelength is used for irradiation so as to allow most photosensitive monomers to be polymerized as polymer. Lastly, a ultra-violet with a second wavelength is used for irradiation, wherein the second wavelength is larger than the first wavelength so as to allow residual photosensitive monomers to be polymerized.
    Type: Application
    Filed: August 3, 2009
    Publication date: March 4, 2010
    Applicant: AU OPTRONICS CORP.
    Inventors: Chung-Ching Hsieh, Chia-Hsuan Pai, Cheng-Wei Huang, Te-Sheng Chen, Norio Sugiura
  • Publication number: 20100007004
    Abstract: A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad.
    Type: Application
    Filed: July 10, 2009
    Publication date: January 14, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsiao Chuan CHANG, Tsung Yueh Tsai, Yi Shao Lai, Ho Ming Tong, Jian cheng Chen, Wei Chi Yih, Chang Ying Hung, Cheng Wei Huang, Chih Hsing Chen, Tai Yuan Huang, Chieh Ting Chen, Yi Tsai Lu
  • Publication number: 20090300376
    Abstract: Provided is a control method for an advanced configuration and power interface (ACPI) in a computer system. The computer system comprises a processor and a bus master, wherein the processor, as defined by the ACPI specification, has a first state (C0 state), a second state (C1 state), a third state (C2 state), a fourth state (C3 state) and a fifth state (C4 state). The method comprises enabling the processor to run in the C2 state when a request from the bus master is issued before the processor enters the C3 state, or enables the processor to ignore the C4 state and complete the C3 state when the request from the bus master is issued at the C3 state and before entering the C4 state.
    Type: Application
    Filed: September 12, 2008
    Publication date: December 3, 2009
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Jen-Po Chang, Grace Qin, Cheng-Wei Huang, Ying-Chung Chen
  • Patent number: 7620826
    Abstract: Thermal throttling duty estimation methods for a CPU (Central Processing Unit) in a computer system are provided. The temperature of a CPU is highly related to the CPU performance. CPU temperature data (CPUT) is first acquired. A thermal throttle duty (TTD) is then calculated according to the acquired CPUT. Thereafter, the calculated TTD can be sent to the CPU and the CPU performance is accordingly adjusted.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: November 17, 2009
    Assignee: Via Technologies, Inc.
    Inventors: Cheng-Wei Huang, Chia-Ming Hsu, Hao-Lin Lin, Wen-Juin Huang
  • Publication number: 20090256682
    Abstract: A product managing system and method using RFID technology is provided. The product managing system includes an RFID tag, an RFID reader, and a server. The RFID tag is set on a product for providing a tag ID, an object type and attribute, and an event content. The RFID reader reads the RFID tag. The server obtains various information provided by the RFID tag set on the product from the RFID reader, determines the product ID according to the tag ID, determines a class of the product and whether the product is correctly combined with another product according to the object type and attribute, and determines whether a processing procedure of the product is correctly conducted according to the event content. The server finally determines whether the product is normal according to the aforementioned determinations.
    Type: Application
    Filed: June 5, 2009
    Publication date: October 15, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Mengru (Arthur) Tu, Jen-Yau Kuo, Kuo-Shu Lo, Cheng-Wei Huang, Li-Dien Fu