Patents by Inventor Cheng-Wei Luo

Cheng-Wei Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11450599
    Abstract: An integrated circuit is provided. The integrated circuit includes a first trace, a second trace and a third trace. The first trace, the second trace and the third trace are each a continuous trace. The first trace, the second trace and the third trace together use only two conductor layers of a semiconductor structure. In a crossing area of the first trace, the second trace and the third trace, the first trace crosses the second trace once, the first trace crosses the third trace once, and the second trace crosses the third trace once.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: September 20, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Wei Luo, Chieh-Pin Chang, Kai-Yi Huang, Ta-Hsun Yeh
  • Publication number: 20220270812
    Abstract: An inductor and an integrated circuit are provided. The inductor includes a first coil, a second coil, and a third coil. The first coil has a first input terminal and a first output terminal, and the first coil is winded in a first direction from the first input terminal to the first output terminal. The second has a second input terminal and a second output terminal, and the second coil is winded in a second direction which is opposite to the first direction from the second input terminal to the second output terminal. The third has a third input terminal and a third output terminal, and the third input terminal is connected to the first input terminal and the second input terminal.
    Type: Application
    Filed: April 13, 2021
    Publication date: August 25, 2022
    Inventors: Chieh-Pin CHANG, Cheng-Wei LUO, Kai-Yi HUANG, Ta-Hsun YEH
  • Publication number: 20220208437
    Abstract: The present invention discloses an inductor apparatus. Each of a first section of a second and a fourth quadrant loops are bridged to a first section of a former quadrant loop and are bridged to a third section to a second section of a diagonal quadrant loop. Each of a second section of the second and the fourth quadrant loops are coupled to a third section of the diagonal quadrant loop, and to the second section of a former quadrant loop. A first section of a third quadrant loop is coupled to a first section of the fourth quadrant loop, and to a third section of the first quadrant loop. The second section of the third quadrant loop is coupled to a second section of the fourth quadrant loop and to a third section of the third quadrant loop, and to a third section of the first quadrant loop.
    Type: Application
    Filed: December 15, 2021
    Publication date: June 30, 2022
    Inventors: CHENG-WEI LUO, CHIEH-PIN CHANG, KAI-YI HUANG, TA-HSUN YEH
  • Patent number: 11355432
    Abstract: Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Hsiao-Tsung Yen, Chin-Wei Kuo, Cheng-Wei Luo, Kung-Hao Liang
  • Patent number: 11302470
    Abstract: A semiconductor element includes a first coil substantially located at a first plane; a second coil substantially located at the first plane; a connecting section that connects the first coil and the second coil; a third coil substantially located at a second plane different from the first plane; and a fourth coil substantially located at the second plane. The third coil and the first coil are connected through a through structure, and the fourth coil and the second coil are connected through a through structure. The third coil and the fourth are not directly connected.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: April 12, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Publication number: 20220077083
    Abstract: A semiconductor structure includes a first inductor, a second inductor, and a first input/output (I/O) pad. The first I/O pad is coupled to the first inductor and the second inductor. The first I/O pad, a first central axis of a first magnetic field of the first inductor, and a second central axis of a second magnetic field of the second inductor are disposed sequentially along a first direction.
    Type: Application
    Filed: March 31, 2021
    Publication date: March 10, 2022
    Inventors: CHENG-WEI LUO, CHIEH-PIN CHANG, KAI-YI HUANG, TA-HSUN YEH
  • Patent number: 11250985
    Abstract: A semiconductor element includes a first spiral coil, a second spiral coil, a connecting section, a first guide segment, and a second guide segment. The first spiral coil is formed with a first end and a second end, and includes a first inner turn and a first outer turn. The first inner turn is located in a range surrounded by the outer turn, and the first end and the second end are located at the first inner turn. The second spiral coil and the first spiral coil are located in substantially a same metal layer. The connecting section connects the first spiral coil and the second spiral coil. The first guide segment is connected to the first end. The second guide segment is connected to the second end. The first guide segment and the second guide segment are fabricated in a metal layer different from a metal layer of the first spiral coil.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: February 15, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Publication number: 20210366643
    Abstract: A method of making a slow wave inductive structure includes depositing a first dielectric layer over a first substrate. The method further includes forming a first conductive winding in the first dielectric layer. The method further includes bonding a second substrate to the first dielectric layer, wherein the second substrate is physically separated from the first conductive winding, and the second substrate has a thickness ranging from about 50 nanometers (nm) to about 150 nm. The method further includes depositing a second dielectric layer over the second substrate. The method further includes forming a second conductive winding in the second dielectric layer, wherein the second substrate is physically separated from the second conductive winding.
    Type: Application
    Filed: August 5, 2021
    Publication date: November 25, 2021
    Inventors: Hsiao-Tsung YEN, Cheng-Wei LUO
  • Publication number: 20210349644
    Abstract: A device for managing storage resources includes a plurality of servers with storage devices, a setting module, a first establishing module, and a second establishing module. The setting module includes a plurality of first storage devices in each server to be a virtual hard disk. When any other storage device of a server is damaged, the storage managing device maps the virtual hard disk with a new storage device and establishes a logical storage device, to perform data access operations on the logical storage device. A related method and a related non-transitory storage medium are also provided.
    Type: Application
    Filed: May 28, 2020
    Publication date: November 11, 2021
    Inventor: CHENG-WEI LUO
  • Publication number: 20210327809
    Abstract: A tank circuit structure includes a first gate layer, a first substrate, a first shielding layer, a first inductor, a second inductor and a first inter metal dielectric (IMD) layer. The first substrate is over the first gate layer. The first shielding layer is over the first gate layer. The first inductor is over the first shielding layer. The second inductor is below the first substrate. The first IMD layer is between the first substrate and the first shielding layer.
    Type: Application
    Filed: July 1, 2021
    Publication date: October 21, 2021
    Inventors: Hsiao-Tsung YEN, Cheng-Wei LUO
  • Patent number: 11101061
    Abstract: A method of making a slow wave inductive structure includes forming a first conductive winding over a first substrate. The method further includes bonding a second substrate to the first substrate, wherein the second substrate has a thickness ranging from about 50 nanometers (nm) to about 150 nm, wherein a distance between the first conductive winding and the second substrate ranges from about 1 micron (?m) to about 2 ?m.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo
  • Patent number: 11088071
    Abstract: A tank circuit structure includes a first gate layer, a first substrate, a first shielding layer, a first conductive line and a first inter metal dielectric (IMD) layer. The first substrate is over the first gate layer. The first shielding layer is over the first substrate. The first conductive line is over the first shielding layer. The first IMD layer is between the first substrate and the first conductive line.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo
  • Publication number: 20210217695
    Abstract: An integrated circuit is provided. The integrated circuit includes a first trace, a second trace and a third trace. The first trace, the second trace and the third trace are each a continuous trace. The first trace, the second trace and the third trace together use only two conductor layers of a semiconductor structure. In a crossing area of the first trace, the second trace and the third trace, the first trace crosses the second trace once, the first trace crosses the third trace once, and the second trace crosses the third trace once.
    Type: Application
    Filed: January 8, 2021
    Publication date: July 15, 2021
    Inventors: CHENG-WEI LUO, CHIEH-PIN CHANG, KAI-YI HUANG, TA-HSUN YEH
  • Publication number: 20210202687
    Abstract: An integrated inductor is provided. The integrated inductor includes a first winding and a second winding, and has a first end, a second end, and a node. The first winding utilizes the first end and the node as two ends thereof and includes a first coil and a second coil, which do not overlap. The second winding utilizes the second end and the node as two ends thereof and includes a third coil and a fourth coil, which do not overlap. The first coil and the third coil have an overlapping area, and the second coil and the fourth coil have an overlapping area. The first coil is surrounded by the third coil, and the fourth coil is surrounded by the second coil.
    Type: Application
    Filed: December 28, 2020
    Publication date: July 1, 2021
    Inventors: CHENG-WEI LUO, CHIEH-PIN CHANG, KAI-YI HUANG, TA-HSUN YEH
  • Publication number: 20210193367
    Abstract: An integrated stack transformer is provided, wherein the integrated stack transformer includes a first winding, a second winding and a third winding implemented by a first metal layer, and a fourth winding and a fifth winding implemented by a second metal layer. The second winding is positioned between the first winding and the third winding, the fourth winding substantially overlaps the first winding, the fifth winding substantially overlaps the third winding, and a distance between the fifth winding and the fourth winding is less than a distance between the third winding and the first winding. The first winding, the third winding, the fourth winding and the fifth winding form a part of one of a primary inductor and a secondary inductor of the integrated stack transformer, and the second winding is a part of the other of the primary inductor and the secondary inductor.
    Type: Application
    Filed: December 8, 2020
    Publication date: June 24, 2021
    Inventors: Kai-Yi Huang, Cheng-Wei Luo, Chieh-Pin Chang, Ta-Hsun Yeh
  • Publication number: 20210090775
    Abstract: Inductor device includes first and a second coils. First coil is wound into plural first circles. Second coil is wound into plural second circles. First connection member is coupled to first circle between outermost and innermost sides among first circles located at first area and first circle on outermost side among first circles located at second area. Second connection member is coupled to second circle on outermost side among second circles located at first area and second circle between outermost and innermost sides among second circles located at second area. At least two first circles of first circles are located at first area, and half of first circle of first circles is located at second area. Half of second circle of second circles is located at first area, and at least two second circles of second circles are located at second area.
    Type: Application
    Filed: September 17, 2020
    Publication date: March 25, 2021
    Inventors: Chieh-Pin CHANG, Cheng-Wei LUO, Kai-Yi HUANG, Ta-Hsun YEH
  • Publication number: 20210090782
    Abstract: An inductor device includes a first coil and a second coil. The first coil includes a first connection member and a plurality of first circles. At least two first circles of the first circles are located at a first area, and half of the first circle of the first circles is located at a second area. The second coil includes a second connection member and a plurality of second circles. At least two second circles of the second circles are located at the second area, and half of the second circle of the second circles is located at the first area. The first connection member is coupled to the at least two first circles and the half of the first circle. The second connection member is coupled to the at least two second circles and the half of the second circle.
    Type: Application
    Filed: September 17, 2020
    Publication date: March 25, 2021
    Inventors: Cheng-Wei LUO, Chieh-Pin CHANG, Kai-Yi HUANG, Ta-Hsun YEH
  • Patent number: 10943730
    Abstract: A single-ended inductor comprises a first partial coil wound in a first direction; and a second partial coil wound in a second direction and adjoined the first partial coil; wherein, the second direction is opposite to the first direction to reduce the coupling of single-ended inductors and peripheral lines and reduce signal interference.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: March 9, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Cheng Wei Luo, Hsiao-Tsung Yen, Ta-Hsun Yeh, Yuh-Sheng Jean
  • Publication number: 20200395166
    Abstract: An inductor device includes a first coil and a second coil. The first coil is wound into a plurality of first circles, and the second coil is wound into a plurality of second circles. At least two of the second circles are interlaced with at least two of the first circles on a first side. The at least two of the second circles are disposed adjacent to each other on the first side. At least one of the first circles is only interlaced with at least one of the second circles on a second side. At least another one of the first circles is only interlaced with at least another one of the second circles on the second side.
    Type: Application
    Filed: June 3, 2020
    Publication date: December 17, 2020
    Inventors: CHIEH-PIN CHANG, CHENG-WEI LUO, KAI-YI HUANG, TA-HSUN YEH
  • Patent number: 10860386
    Abstract: A method for managing storage resources includes calculating ratios of the quantity of data accessed to the current data occupation of storage unit of each server in a network. The method determines one or more servers each with ratio greater than a first preset value, and determines one or more servers each with ratio less than a second preset value. Next, the method outputs signals to control the servers with ratios each greater than the first preset value to transfer data to the one or more servers with ratios each less than the second preset value, until the ratios of all servers is less than or equal to the first preset value and greater than or equal to the second preset value. A related device for applying the method and a related non-transitory storage medium are also provided.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: December 8, 2020
    Assignee: HONGFUJIN PRECISION ELECTRONICS (TIANJIN) CO., LTD.
    Inventor: Cheng-Wei Luo