Patents by Inventor Cheng-Wei Luo

Cheng-Wei Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200341818
    Abstract: A method for managing storage resources includes calculating ratios of the quantity of data accessed to the current data occupation of storage unit of each server in a network. The method determines one or more servers each with ratio greater than a first preset value, and determines one or more servers each with ratio less than a second preset value. Next, the method outputs signals to control the servers with ratios each greater than the first preset value to transfer data to the one or more servers with ratios each less than the second preset value, until the ratios of all servers is less than or equal to the first preset value and greater than or equal to the second preset value. A related device for applying the method and a related non-transitory storage medium are also provided.
    Type: Application
    Filed: June 18, 2019
    Publication date: October 29, 2020
    Inventor: CHENG-WEI LUO
  • Publication number: 20200321277
    Abstract: A tank circuit structure includes a first gate layer, a first substrate, a first shielding layer, a first conductive line and a first inter metal dielectric (IMD) layer. The first substrate is over the first gate layer. The first shielding layer is over the first substrate. The first conductive line is over the first shielding layer. The first IMD layer is between the first substrate and the first conductive line.
    Type: Application
    Filed: June 18, 2020
    Publication date: October 8, 2020
    Inventors: Hsiao-Tsung YEN, Cheng-Wei LUO
  • Publication number: 20200286826
    Abstract: Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Hsiao-Tsung YEN, Chin-Wei Kuo, Cheng-Wei Luo, Kung-Hao Liang
  • Patent number: 10748701
    Abstract: An inductor device includes a first and a second inductor unit. The first inductor unit includes a first and a second wire. The first wire is winded to form circles. The second wire is winded with the first wire to form circles. The first and/or the second wire are winded in an interlaced manner at a first terminal, a second terminal, a first side, and a second side. The second inductor unit includes a third and a fourth wire. The third wire is winded to form circles. The fourth wire is winded with the third wire to form circles. The third and/or the fourth wire are winded in an interlaced manner at a third terminal, a fourth terminal, a third side, and a fourth side. The first wired is coupled to the fourth wired, and the second wired is coupled to the third wired.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 18, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10720387
    Abstract: A tank circuit structure includes a first gate layer, a first substrate, a first shielding layer, a first conductive line and a first inter metal dielectric (IMD) layer. The first substrate is over the first gate layer. The first shielding layer is over the first substrate. The first conductive line is over the first shielding layer. The first IMD layer is between the first substrate and the first conductive line.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo
  • Patent number: 10665539
    Abstract: Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsiao-Tsung Yen, Chin-Wei Kuo, Cheng-Wei Luo, Kung-Hao Liang
  • Publication number: 20200105459
    Abstract: A semiconductor element includes a first coil substantially located at a first plane; a second coil substantially located at the first plane; a connecting section that connects the first coil and the second coil; a third coil substantially located at a second plane different from the first plane; and a fourth coil substantially located at the second plane. The third coil and the first coil are connected through a through structure, and the fourth coil and the second coil are connected through a through structure. The third coil and the fourth are not directly connected.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 2, 2020
    Inventors: HSIAO-TSUNG YEN, CHENG-WEI LUO, YUH-SHENG JEAN, TA-HSUN YEH
  • Publication number: 20200105460
    Abstract: A semiconductor element includes a first spiral coil, a second spiral coil, a connecting section, a first guide segment, and a second guide segment. The first spiral coil is formed with a first end and a second end, and includes a first inner turn and a first outer turn. The first inner turn is located in a range surrounded by the outer turn, and the first end and the second end are located at the first inner turn. The second spiral coil and the first spiral coil are located in substantially a same metal layer. The connecting section connects the first spiral coil and the second spiral coil. The first guide segment is connected to the first end. The second guide segment is connected to the second end. The first guide segment and the second guide segment are fabricated in a metal layer different from a metal layer of the first spiral coil.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 2, 2020
    Inventors: HSIAO-TSUNG YEN, CHENG-WEI LUO, YUH-SHENG JEAN, TA-HSUN YEH
  • Publication number: 20200090849
    Abstract: A slow wave inductive structure includes a first substrate. The slow wave inductive structure further includes a first conductive winding over the first substrate. The slow wave inductive structure further includes a second substrate over the first substrate, wherein a distance between the first conductive winding and the second substrate ranges from about 1 micron (?m) to about 2 ?m, and the second substrate comprises polysilicon or doped silicon. The slow wave inductive structure further includes a second conductive winding on an opposite side of the second substrate from the first conductive winding.
    Type: Application
    Filed: November 20, 2019
    Publication date: March 19, 2020
    Inventors: Hsiao-Tsung YEN, Cheng-Wei LUO
  • Patent number: 10593464
    Abstract: A semiconductor element includes a first coil substantially located at a first plane; a second coil substantially located at the first plane; a connecting section that connects the first coil and the second coil; a third coil substantially located at a second plane different from the first plane; and a fourth coil substantially located at the second plane. The third coil and the first coil are connected through a through structure, and the fourth coil and the second coil are connected through a through structure. The third coil and the fourth are not directly connected.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: March 17, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10580568
    Abstract: A semiconductor element includes a first spiral coil, a second spiral coil, a connecting section, a first guide segment, and a second guide segment. The first spiral coil is formed with a first end and a second end, and includes a first inner turn and a first outer turn. The first inner turn is located in a range surrounded by the outer turn, and the first end and the second end are located at the first inner turn. The second spiral coil and the first spiral coil are located in substantially a same metal layer. The connecting section connects the first spiral coil and the second spiral coil. The first guide segment is connected to the first end. The second guide segment is connected to the second end. The first guide segment and the second guide segment are fabricated in a metal layer different from a metal layer of the first spiral coil.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: March 3, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10510476
    Abstract: A slow wave inductive structure includes a first substrate, a first conductive winding over the first substrate, and a second substrate over the first substrate. The second substrate has a thickness ranging from about 50 nanometers (nm) to about 150 nm. A distance between the first conductive winding and the second substrate ranges from about 1 micron (?m) to about 2 ?m. A slow wave inductor includes a first substrate and a first conductive winding over the first substrate. The slow wave inductor further includes a second substrate over the first substrate and a plurality of switches in the second conductive substrate. The first conductive winding is connected to each switch of the plurality of switches.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo
  • Patent number: 10497507
    Abstract: A semiconductor element fabricated in a semiconductor structure and coupled to an application circuit through at least two connecting terminals. The semiconductor element includes a first spiral coil, a second spiral coil and a connecting portion. The first spiral coil is substantially located in a first metal layer and formed with a first end and a second end. The second spiral coil is substantially located in the first metal layer and formed with a third end and a fourth end. The connecting portion, which is located in a second metal layer, connects the second end and the fourth end. The first end is used as one of the two connecting terminals and the third end is used as the other of the two connecting terminals. The second metal layer is different from the first metal layer.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: December 3, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10483937
    Abstract: A transceiver circuit including: a substrate; a signal coupler configured on the substrate and including a coiled first conductive layer pattern; and a notch filter configured on the substrate and including a coiled second conductive layer pattern; wherein each of the first conductive layer pattern and the second conductive layer pattern is arranged as a substantially symmetrical pattern with respect to a first virtual axis.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: November 19, 2019
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Jian-You Chen, Cheng-Wei Luo, Kuan-Yu Shih
  • Patent number: 10373954
    Abstract: A FinFET that includes a semiconductor substrate that has insulating areas, a fin structure, a gate dielectric layer, a gate electrode structure, a drain structure and a source structure is provided. The fin structure is disposed to extend on the semiconductor substrate between two insulating areas. The gate dielectric layer is disposed to extend across two sides of the fin structure. The gate electrode structure is disposed on the gate dielectric layer. The drain structure is disposed at a first side of the gate electrode structure and has a first resistance relative to the gate electrode. The source structure is disposed at a second side of the gate electrode structure and has a second resistance relative to the gate electrode. The first resistance is larger than the second resistance.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: August 6, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ta-Hsun Yeh, Cheng-Wei Luo, Hsiao-Tsung Yen, Yuh-Sheng Jean
  • Patent number: 10340193
    Abstract: A fin field-effect transistor is provided. The fin field-effect transistor includes a substrate, a fin structure, a gate-stacked structure, and an isolation structure. The fin structure is disposed on the substrate, and the gate-stacked structure covers the fin structure. The isolation structure disposed on the substrate to isolate the gate-stacked structure from the substrate has different thicknesses in different portions.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: July 2, 2019
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Ta-Hsun Yeh, Cheng-Wei Luo, Hsiao-Tsung Yen, Yuh-Sheng Jean
  • Publication number: 20190165751
    Abstract: A transceiver circuit including: a substrate; a signal coupler configured on the substrate and including a coiled first conductive layer pattern; and a notch filter configured on the substrate and including a coiled second conductive layer pattern; wherein each of the first conductive layer pattern and the second conductive layer pattern is arranged as a substantially symmetrical pattern with respect to a first virtual axis.
    Type: Application
    Filed: September 27, 2018
    Publication date: May 30, 2019
    Inventors: JIAN-YOU CHEN, CHENG-WEI LUO, KUAN-YU SHIH
  • Patent number: 10262782
    Abstract: An 8-shaped integrated inductor includes a first terminal; a second terminal; a third terminal; a bridging structure that includes a first metal segment and a second metal segment, the first metal segment and the second metal segment being disposed in different layers of a semiconductor structure and partially overlapping; a first sensing unit employing the first terminal and the third terminal as its two terminals and including the first metal segment; and a second sensing unit employing the second terminal and the third terminal as its two terminals and including the second metal segment and a third metal segment. The third metal segment is disposed at a metal layer different from the second metal segment and conductively connecting other metal segments of the second sensing unit without crossing the metal segments of the first sensing unit.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: April 16, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Publication number: 20190108935
    Abstract: An 8-shaped integrated inductor includes a first terminal; a second terminal; a third terminal; a bridging structure that includes a first metal segment and a second metal segment, the first metal segment and the second metal segment being disposed in different layers of a semiconductor structure and partially overlapping; a first sensing unit employing the first terminal and the third terminal as its two terminals and including the first metal segment; and a second sensing unit employing the second terminal and the third terminal as its two terminals and including the second metal segment and a third metal segment. The third metal segment is disposed at a metal layer different from the second metal segment and conductively connecting other metal segments of the second sensing unit without crossing the metal segments of the first sensing unit.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 11, 2019
    Inventors: HSIAO-TSUNG YEN, CHENG-WEI LUO, YUH-SHENG JEAN, TA-HSUN YEH
  • Publication number: 20190057965
    Abstract: A FinFET that includes a semiconductor substrate that has insulating areas, a fin structure, a gate dielectric layer, a gate electrode structure, a drain structure and a source structure is provided. The fin structure is disposed to extend on the semiconductor substrate between two insulating areas. The gate dielectric layer is disposed to extend across two sides of the fin structure. The gate electrode structure is disposed on the gate dielectric layer. The drain structure is disposed at a first side of the gate electrode structure and has a first resistance relative to the gate electrode. The source structure is disposed at a second side of the gate electrode structure and has a second resistance relative to the gate electrode. The first resistance is larger than the second resistance.
    Type: Application
    Filed: October 23, 2018
    Publication date: February 21, 2019
    Inventors: Ta-Hsun YEH, Cheng-Wei LUO, Hsiao-Tsung YEN, Yuh-Sheng JEAN